Datasheet > CY7C1292DV18-300BZC

CY7C1292DV18-300BZC

更新时间： 2024-12-01 14:48:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
23页	279K
描述
QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1292DV18-300BZC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	BGA	包装说明：	LBGA,
针数：	165	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.92	Is Samacsys：	N
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	15 mm	内存密度：	18874368 bit
内存集成电路类型：	QDR SRAM	内存宽度：	18
功能数量：	1	端子数量：	165
字数：	1048576 words	字数代码：	1000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	1MX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装形状：	RECTANGULAR	封装形式：	GRID ARRAY, LOW PROFILE
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	240
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	TIN LEAD	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	30	宽度：	13 mm
Base Number Matches：	1

CY7C1292DV18-300BZC 数据手册

浏览型号CY7C1292DV18-300BZC的Datasheet PDF文件第2页

浏览型号CY7C1292DV18-300BZC的Datasheet PDF文件第3页

浏览型号CY7C1292DV18-300BZC的Datasheet PDF文件第4页

浏览型号CY7C1292DV18-300BZC的Datasheet PDF文件第5页

浏览型号CY7C1292DV18-300BZC的Datasheet PDF文件第6页

CY7C1292DV18

CY7C1294DV18

PRELIMINARY

9-Mbit QDR-II™ SRAM 2-Word

Burst Architecture

Configurations

Features

CY7C1292DV18 – 1M x 18

CY7C1294DV18 – 512K x 36

• Separate Independent Read and Write data ports

— Supports concurrent transactions

• 300-MHz clock for high bandwidth

• 2-Word Burst on all accesses

Functional Description

The CY7C1292DV18, and CY7C1294DV18 are 1.8V

Synchronous Pipelined SRAMs, equipped with QDR™-II

architecture. QDR-II architecture consists of two separate

ports to access the memory array. The Read port has

dedicated Data Outputs to support Read operations and the

Write Port has dedicated Data Inputs to support Write opera-

tions. QDR-II architecture has separate data inputs and data

outputs to completely eliminate the need to “turn-around” the

data bus required with common I/O devices. Access to each

port is accomplished through a common address bus. The

Read address is latched on the rising edge of the K clock and

the Write address is latched on the rising edge of the K clock.

Accesses to the QDR-II Read and Write ports are completely

independent of one another. In order to maximize data

throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with 18-bit words (CY7C1292DV18) or 36-bit

words (CY7C1294DV18) that burst sequentially into or out of

the device. Since data can be transferred into and out of the

device on every rising edge of both input clocks (K and K and

C and C), memory bandwidth is maximized while simplifying

system design by eliminating bus “turn-arounds.”

• Double Data Rate (DDR) interfaces on both Read and

Write ports (data transferred at 600 MHz) @ 300 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mismatching

• Echo clocks (CQ and CQ) simplify data capture in

high-speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in x18 and x36 configurations

• Full data coherency, providing most current data

• Core V_DD= 1.8V (±0.1V); I/O V_DDQ= 1.4V to V_DD

• 13 x 15 x 1.4 mm 1.0-mm pitch FBGA package, 165 ball

(11x15 matrix)

• Offered in both lead-free and non-lead free packages

• Variable drive HSTL output buffers

Depth expansion is accomplished with Port Selects for each

port. Port selects allow each port to operate independently.

• JTAG 1149.1 compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C (or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Cypress Semiconductor Corporation

Document #:001-00350 Rev. **

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised June 6, 2005

12 3 4 5 6 7...23

中文翻译

下载PDF

与CY7C1292DV18-300BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1292DV18-300BZI	CYPRESS	获取价格	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, FBGA-165
CY7C1292DV18-300BZXC	CYPRESS	获取价格	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CY7C1292DV18-300BZXI	CYPRESS	获取价格	QDR SRAM, 1MX18, 0.45ns, CMOS, PBGA165, 13 X 15 MM, 1.40 MM HEIGHT, LEAD FREE, FBGA-165
CY7C1294DV18	CYPRESS	获取价格	9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur
CY7C1294DV18-167BZC	CYPRESS	获取价格	9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur
CY7C1294DV18-167BZI	CYPRESS	获取价格	9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur
CY7C1294DV18-167BZXC	CYPRESS	获取价格	9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur
CY7C1294DV18-167BZXI	CYPRESS	获取价格	9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur
CY7C1294DV18-200BZC	CYPRESS	获取价格	9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur
CY7C1294DV18-200BZI	CYPRESS	获取价格	9-Mbit QDR- II⑩ SRAM 2-Word Burst Architectur

与CY7C1292DV18-300BZC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

53
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

42
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

70
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

66

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1292DV18-300BZC

CY7C1292DV18-300BZC 技术参数

CY7C1292DV18-300BZC 数据手册

与CY7C1292DV18-300BZC相关器件

与CY7C1292DV18-300BZC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1292DV18-300BZC

CY7C1292DV18-300BZC 技术参数

CY7C1292DV18-300BZC 数据手册

与CY7C1292DV18-300BZC相关器件

与CY7C1292DV18-300BZC相关文章

您还可以找

您在本页遇到什么问题？