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CY7C128A-45DMB PDF预览

CY7C128A-45DMB

更新时间： 2024-11-30 00:01:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 221K
描述
2K x 8 Static RAM

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中文翻译

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CY7C128A-45DMB 数据手册

 浏览型号CY7C128A-45DMB的Datasheet PDF文件第2页浏览型号CY7C128A-45DMB的Datasheet PDF文件第3页浏览型号CY7C128A-45DMB的Datasheet PDF文件第4页浏览型号CY7C128A-45DMB的Datasheet PDF文件第5页浏览型号CY7C128A-45DMB的Datasheet PDF文件第6页浏览型号CY7C128A-45DMB的Datasheet PDF文件第7页 
1CY7C128A  
CY7C128A  
2K x 8 Static RAM  
Features  
Functional Description  
The CY7C128A is a high-performance CMOS static RAM or-  
ganized as 2048 words by 8 bits. Easy memory expansion is  
provided by an active LOW chip enable (CE), and active LOW  
output enable (OE) and three-state drivers. The CY7C128A  
has an automatic power-down feature, reducing the power  
consumption by 83% when deselected.  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• High speed  
— 15 ns  
• Low active power  
— 440 mW (commercial)  
— 550 mW (military)  
Writing to the device is accomplished when the chip enable  
(CE) and write enable (WE) inputs are both LOW.  
Data on the eight I/O pins (I/O through I/O ) is written into the  
• Low standby power  
— 110 mW  
0
7
memory location specified on the address pins (A through  
0
A
).  
10  
• TTL-compatible inputs and outputs  
• Capable of withstanding greater than 2001V electro-  
static discharge  
Reading the device is accomplished by taking chip enable  
(CE) and output enable (OE) LOW while write enable (WE) remains  
HIGH. Under these conditions, the contents of the memory location  
specified on the address pins will appear on the eight I/O pins.  
• V of 2.2V  
IH  
The I/O pins remain in high-impedance state when chip enable  
(CE) or output enable (OE) is HIGH or write enable (WE) is LOW.  
The CY7C128A utilizes a die coat to insure alpha immunity.  
Pin  
Logic Block Diagram  
Configurations  
DIP/SOJ  
Top View  
A
V
CC  
1
24  
23  
22  
7
A
A
A
A
8
A
9
2
3
4
5
6
7
8
9
6
5
4
WE  
OE  
21  
20  
19  
18  
17  
A
A
2
3
A
10  
7C128A  
A
1
CE  
I/O  
A
0
7
I/O  
I/O  
0
I/O  
6
16  
15  
14  
13  
0
INPUT BUFFER  
I/O  
I/O  
10  
11  
12  
I/O  
I/O  
5
4
1
2
I/O  
1
A
10  
GND  
I/O  
3
A
9
I/O  
2
C128A–2  
A
8
LCC  
Top View  
A
7
I/O  
3
128 x 16 x 8  
ARRAY  
A
6
I/O  
4
A
5
A
4
3
2 1 2423  
22  
I/O  
5
4
A
4
A
9
5
6
7
8
9
10  
21  
20  
19  
18  
17  
16  
A
2
WE  
OE  
3
A
CE  
WE  
I/O  
6
POWER  
DOWN  
A
A
10  
7C128A  
1
COLUMN  
DECODER  
A
0
CE  
I/O  
0
I/O  
7
I/O  
7
OE  
I/O  
1
I/O  
6
11 12 13 14 15  
A
3
A
2
A
1
A
0
C128A–3  
C128A–1  
Selection Guide  
7C128A–15 7C128A–20 7C128A–25  
7C128A–35  
7C128A–45  
Maximum Access Time (ns)  
15  
20  
25  
100  
125  
20  
35  
100  
100  
20  
45  
Commercial  
Military  
120  
100  
Maximum Operating  
Current (mA)  
125  
100  
20  
Commercial  
Military  
40/40  
40/20  
40/20  
Maximum Standby  
Current (mA)  
40  
20  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
December 1988 – Revised December 1992  
1234567...9

中文翻译

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CY7C128A-45SC CYPRESS

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CY7C128A-45VC CYPRESS

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CY7C128A-45VCR CYPRESS

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 		Standard SRAM, 2KX8, 45ns, CMOS, PDSO24, PLASTIC, SOJ-24
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 		Standard SRAM, 2KX8, 45ns, CMOS, PDSO24, 0.300 INCH, PLASTIC, SOJ-24
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 		Standard SRAM, 2KX8, 55ns, CMOS, CDIP24, 0.300 INCH, CERDIP-24
CY7C128A-55KMB CYPRESS

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