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CY7C1061DV33_07 PDF预览

CY7C1061DV33_07

更新时间: 2024-11-09 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 542K
描述
16-Mbit (1M x 16) Static RAM

CY7C1061DV33_07 数据手册

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CY7C1061DV33  
16-Mbit (1M x 16) Static RAM  
Features  
Functional Description  
High speed  
tAA = 10 ns  
The CY7C1061DV33 is a high performance CMOS Static RAM  
organized as 1,048,576 words by 16 bits.  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from IO pins (IO0 through IO7), is written  
into the location specified on the address pins (A0 through A19).  
If Byte High Enable (BHE) is LOW, then data from IO pins (IO8  
through IO15) is written into the location specified on the address  
pins (A0 through A19).  
Low active power  
ICC = 175 mA at 10 ns  
Low CMOS standby power  
ISB2 = 25 mA  
Operating voltages of 3.3 ± 0.3V  
2.0V data retention  
To read from the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appears  
on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on IO8 to IO15. See the Truth Table on page 9  
for a complete description of Read and Write modes.  
Automatic power down when deselected  
TTL compatible inputs and outputs  
Easy memory expansion with CE1 and CE2 features  
Available in Pb-free 54-Pin TSOP II and 48-Ball VFBGA  
packages  
The input or output pins (IO0 through IO15) are placed in a high  
impedance state when the device is deselected (CE1 HIGH/CE2  
LOW), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE1  
LOW, CE2 HIGH, and WE LOW).  
The CY7C1061DV33 is available in a 54-Pin TSOP II package  
with center power and ground (revolutionary) pinout, and a  
48-Ball VFBGA package.  
Logic Block Diagram  
INPUT BUFFER  
A
0
A
1
A
2
A
4
3
IO0 – IO7  
1M x 16  
ARRAY  
A
A
5
IO8 – IO15  
A
6
A
7
A
8
A
9
COLUMN  
DECODER  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 38-05476 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 06, 2007  

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