5秒后页面跳转
捷配首页

Datasheet > CY7C1061DV33-10BV1XIT
CY7C1061DV33-10BV1XIT PDF预览

CY7C1061DV33-10BV1XIT

更新时间： 2024-11-09 14:33:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
19页 1632K
描述
Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48

阅读下载

中文翻译

获取价格

CY7C1061DV33-10BV1XIT 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete包装说明：VFBGA, BGA48,6X8,30
Reach Compliance Code：compliantECCN代码：3A991.B.2.B
HTS代码：8542.32.00.41风险等级：5.82
Is Samacsys：N最长访问时间：10 ns
I/O 类型：COMMONJESD-30 代码：R-PBGA-B48
JESD-609代码：e1长度：9.5 mm
内存密度：16777216 bit内存集成电路类型：STANDARD SRAM
内存宽度：16湿度敏感等级：3
功能数量：1端子数量：48
字数：1048576 words字数代码：1000000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：1MX16
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装等效代码：BGA48,6X8,30
封装形状：RECTANGULAR封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1 mm最大待机电流：0.025 A
最小待机电流：2 V子类别：SRAMs
最大压摆率：0.175 mA最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Silver/Copper (Sn/Ag/Cu)
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM处于峰值回流温度下的最长时间：20
宽度：8 mmBase Number Matches：1

CY7C1061DV33-10BV1XIT 数据手册

 浏览型号CY7C1061DV33-10BV1XIT的Datasheet PDF文件第2页浏览型号CY7C1061DV33-10BV1XIT的Datasheet PDF文件第3页浏览型号CY7C1061DV33-10BV1XIT的Datasheet PDF文件第4页浏览型号CY7C1061DV33-10BV1XIT的Datasheet PDF文件第5页浏览型号CY7C1061DV33-10BV1XIT的Datasheet PDF文件第6页浏览型号CY7C1061DV33-10BV1XIT的Datasheet PDF文件第7页 
CY7C1061DV33  
16-Mbit (1M × 16) Static RAM  
16-Mbit (1M  
× 16) Static RAM  
Features  
Functional Description  
■ High speed  
❐ tAA = 10 ns  
The CY7C1061DV33 is a high performance CMOS Static RAM  
organized as 1,048,576 words by 16 bits.  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0 through  
■ Low active power  
❐ ICC = 175 mA at 100 MHz  
■ Low CMOS standby power  
❐ ISB2 = 25 mA  
A
19). If Byte High Enable (BHE) is LOW, then data from I/O pins  
(I/O8 through I/O15) is written into the location specified on the  
address pins (A0 through A19).  
■ Operating voltages of 3.3 ± 0.3 V  
■ 2.0 V data retention  
To read from the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appears  
on I/O0 to I/O7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on I/O8 to I/O15. See Truth Table on page 12  
for a complete description of Read and Write modes.  
■ Automatic power down when deselected  
■ TTL compatible inputs and outputs  
■ Easy memory expansion with CE1 and CE2 features  
■ Available in Pb-free 54-pin TSOP II and 48-ball VFBGA  
packages  
The input or output pins (I/O0 through I/O15) are placed in a high  
impedance state when the device is deselected (CE1 HIGH/CE2  
LOW), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE1  
LOW, CE2 HIGH, and WE LOW).  
■ Offered in single CE and dual CE options  
The CY7C1061DV33 is available in a 54-pin TSOP II package  
with center power and ground (revolutionary) pinout, and 48-ball  
VFBGA packages.  
For a complete list of related documentation, click here.  
Logic Block Diagram  
INPUT BUFFER  
A
0
A
1
A
2
A
4
3
I/O0 – I/O7  
I/O8 – I/O15  
1M x 16  
ARRAY  
A
A
5
A
6
A
7
A
8
A
9
COLUMN  
DECODER  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 38-05476 Rev. *K  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 22, 2016  
 
 
1234567...19

中文翻译

下载PDF

CY7C1061DV33-10BV1XIT 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1061DV33-10BV1XI CYPRESS

完全替代

 Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1061DV33-10BVJXI CYPRESS

完全替代

 Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1061DV33-10BVXI CYPRESS

完全替代

 16-Mbit (1M x 16) Static RAM

与CY7C1061DV33-10BV1XIT相关器件

型号 品牌 获取价格 描述 数据表
CY7C1061DV33-10BVJXI CYPRESS

获取价格

 		Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1061DV33-10BVJXIT CYPRESS

获取价格

 		Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1061DV33-10BVXI CYPRESS

获取价格

 		16-Mbit (1M x 16) Static RAM
CY7C1061DV33-10ZSXI CYPRESS

获取价格

 		16-Mbit (1M x 16) Static RAM
CY7C1061DV33-10ZXI CYPRESS

获取价格

 		16-Mbit (1M x 16) Static RAM
CY7C1061G CYPRESS

获取价格

 		16-Mbit (1 M words × 16 bit) Static RAM with
CY7C1061G-10BV1XI INFINEON

获取价格

 		Asynchronous SRAM
CY7C1061G-10BV1XIT INFINEON

获取价格

 		Asynchronous SRAM
CY7C1061G-10BVJXI INFINEON

获取价格

 		Asynchronous SRAM
CY7C1061G-10BVJXIT INFINEON

获取价格

 		Asynchronous SRAM

与CY7C1061DV33-10BV1XIT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证