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CY7C1061DV33-10ZSXI PDF预览

CY7C1061DV33-10ZSXI

更新时间: 2024-11-19 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 542K
描述
16-Mbit (1M x 16) Static RAM

CY7C1061DV33-10ZSXI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSOP2
包装说明:TSOP2, TSOP54,.46,32针数:54
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:8.55
最长访问时间:10 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G54JESD-609代码:e3
长度:22.415 mm内存密度:16777216 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:54字数:1048576 words
字数代码:1000000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:1MX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP54,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.025 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.175 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:10.16 mm
Base Number Matches:1

CY7C1061DV33-10ZSXI 数据手册

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CY7C1061DV33  
16-Mbit (1M x 16) Static RAM  
Features  
Functional Description  
High speed  
tAA = 10 ns  
The CY7C1061DV33 is a high performance CMOS Static RAM  
organized as 1,048,576 words by 16 bits.  
To write to the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable  
(BLE) is LOW, then data from IO pins (IO0 through IO7), is written  
into the location specified on the address pins (A0 through A19).  
If Byte High Enable (BHE) is LOW, then data from IO pins (IO8  
through IO15) is written into the location specified on the address  
pins (A0 through A19).  
Low active power  
ICC = 175 mA at 10 ns  
Low CMOS standby power  
ISB2 = 25 mA  
Operating voltages of 3.3 ± 0.3V  
2.0V data retention  
To read from the device, take Chip Enables (CE1 LOW and CE2  
HIGH) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data  
from the memory location specified by the address pins appears  
on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from  
memory appears on IO8 to IO15. See the Truth Table on page 9  
for a complete description of Read and Write modes.  
Automatic power down when deselected  
TTL compatible inputs and outputs  
Easy memory expansion with CE1 and CE2 features  
Available in Pb-free 54-Pin TSOP II and 48-Ball VFBGA  
packages  
The input or output pins (IO0 through IO15) are placed in a high  
impedance state when the device is deselected (CE1 HIGH/CE2  
LOW), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE1  
LOW, CE2 HIGH, and WE LOW).  
The CY7C1061DV33 is available in a 54-Pin TSOP II package  
with center power and ground (revolutionary) pinout, and a  
48-Ball VFBGA package.  
Logic Block Diagram  
INPUT BUFFER  
A
0
A
1
A
2
A
4
3
IO0 – IO7  
1M x 16  
ARRAY  
A
A
5
IO8 – IO15  
A
6
A
7
A
8
A
9
COLUMN  
DECODER  
BHE  
WE  
CE2  
CE1  
OE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 38-05476 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised September 06, 2007  

CY7C1061DV33-10ZSXI 替代型号

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CY7C1061AV33-10ZXI CYPRESS

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