Datasheet > CY7C1061G30

CY7C1061G30

更新时间： 2024-11-24 01:23:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
18页	563K
描述
16-Mbit (1 M words Ã 16 bit) Static RAM with Error-Correcting Code (ECC)

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CY7C1061G30 数据手册

CY7C1061G Automotive

16-Mbit (1 M words × 16 bit) Static RAM

with Error-Correcting Code (ECC)

16-Mbit (1

M words × 16 bit) Static RAM with Error-Correcting Code (ECC)

Features

Functional Description

■ High speed

❐ t_AA= 10 ns

CY7C1061G^[1]is a high-performance CMOS fast static RAM

automotive part with embedded ECC. ECC logic can detect and

correct single-bit error in read data word during read cycles.

■ Temperature range

❐ Automotive-E: –40 °C to 125 °C

This device has single chip enable input and is accessed by

asserting the chip enable input (CE) LOW.

■ Embedded error-correcting code (ECC) for single-bit error

correction

To perform data writes, assert the Write Enable (WE) input LOW

and provide the data and address on the device data pins (I/O₀

through I/O₁₅) and address pins (A₀through A₁₉) respectively.

The Byte High Enable (BHE) and Byte Low Enable (BLE), inputs

control byte writes and write data on the corresponding I/O lines

to the memory location specified. BHE controls I/O₈through

I/O₁₅and BLE controls I/O₀through I/O₇.

■ Low active and standby currents

❐ I_CC= 90-mA typical at 100 MHz

❐ I_SB2= 20-mA typical

■ Operating voltage range: 2.2 V to 3.6 V

■ 1.0-V data retention

To perform data reads, assert the Output Enable (OE) input and

provide the required address on the address lines. Read data is

accessible on I/O lines (I/O₀through I/O₁₅). You can perform

byte accesses by asserting the required byte enable signal (BHE

or BLE) to read either the upper byte or the lower byte of data

from the specified address location.

■ Transistor-transistor logic (TTL) compatible inputs and outputs

■ Available in Pb-free 48-ball VFBGA and 48-pin TSOP I

packages

All I/Os (I/O₀through I/O₁₅) are placed in a high-impedance state

when the device is deselected (CE HIGH), or control signals are

de-asserted (OE, BLE, BHE). Refer to the below logic block

diagram.

The CY7C1061G automotive device is available in 48-ball

VFBGA and 48-pin TSOP I packages.

Logic Block Diagram – CY7C1061G

ECC EN CO D ER

IN PU T BU FFER

A 0

A 1

A 2

A 3

A 4

A 5

A 6

A 7

A 8

A 9

I/O ₀‐I/O ₇

I/O ₈‐I/O ₁₅

M EM O R Y

A RRA Y

CO LU M N D ECO D ER

B H E

W E

O E

B LE

Note

1. The device does not support automatic write-back on error detection.

Cypress Semiconductor Corporation

Document Number: 001-84821 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 28, 2015

12 3 4 5 6 7...18

中文翻译

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与CY7C1061G30相关器件

型号	品牌	获取价格	描述	数据表
CY7C1061G30-10BV1XE	INFINEON	获取价格	Asynchronous SRAM
CY7C1061G30-10BV1XET	INFINEON	获取价格	Asynchronous SRAM
CY7C1061G30-10BV1XI	INFINEON	获取价格	Asynchronous SRAM
CY7C1061G30-10BV1XIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1061G30-10BVJXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1061G30-10BVJXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1061G30-10BVXI	INFINEON	获取价格	Asynchronous SRAM
CY7C1061G30-10BVXIT	INFINEON	获取价格	Asynchronous SRAM
CY7C1061G30-10ZSXI	CYPRESS	获取价格	Standard SRAM, 1MX16, 10ns, CMOS, PDSO54, TSOP2-54
CY7C1061G30-10ZSXI	INFINEON	获取价格	Asynchronous SRAM

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