5秒后页面跳转
捷配首页

Datasheet > 暂无类别数据> CY7C1061BV33-12ZXC
CY7C1061BV33-12ZXC PDF预览

CY7C1061BV33-12ZXC

更新时间： 2024-11-09 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 306K
描述
16-Mbit (1M x 16) Static RAM

阅读下载

中文翻译

获取价格

CY7C1061BV33-12ZXC 数据手册

 浏览型号CY7C1061BV33-12ZXC的Datasheet PDF文件第2页浏览型号CY7C1061BV33-12ZXC的Datasheet PDF文件第3页浏览型号CY7C1061BV33-12ZXC的Datasheet PDF文件第4页浏览型号CY7C1061BV33-12ZXC的Datasheet PDF文件第5页浏览型号CY7C1061BV33-12ZXC的Datasheet PDF文件第6页浏览型号CY7C1061BV33-12ZXC的Datasheet PDF文件第7页 
CY7C1061BV33  
16-Mbit (1M x 16) Static RAM  
Low Enable (BLE) is LOW, then data from I/O pins (I/O0  
through I/O7), is written into the location specified on the  
address pins (A0 through A19). If Byte High Enable (BHE) is  
LOW, then data from I/O pins (I/O8 through I/O15) is written into  
the location specified on the address pins (A0 through A19).  
Features  
• High speed  
— tAA = 10 ns  
• Low active power  
Reading from the device is accomplished by enabling the chip  
by taking CE LOW while forcing the Output Enable (OE) LOW  
and the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is  
LOW, then data from the memory location specified by the  
address pins will appear on I/O0 to I/O7. If Byte High Enable  
(BHE) is LOW, then data from memory will appear on I/O8 to  
I/O15. See the truth table at the back of this data sheet for a  
complete description of Read and Write modes.  
— 990 mW (max.)  
• Operating voltages of 3.3 ± 0.3V  
• 2.0V data retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Available in Pb-free and non Pb-free 54-pin TSOP II  
package  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a Write operation  
(CE LOW and WE LOW).  
Functional Description  
The CY7C1061BV33 is a high-performance CMOS Static  
RAM organized as 1,048,576 words by 16 bits.  
The CY7C1061BV33 is available in a 54-pin TSOP II package  
with center power and ground (revolutionary) pinout.  
Writing to the device is accomplished by enabling the chip (CE  
LOW) while forcing the Write Enable (WE) input LOW. If Byte  
Logic Block Diagram  
Pin Configurations[1, 2]  
54-pin TSOP II (Top View)  
I/O  
V
I/O  
I/O  
1
54  
53  
I/O  
V
11  
12  
CC  
INPUT BUFFER  
2
3
4
5
6
SS  
I/O  
52  
51  
50  
13  
14  
10  
A
0
I/O  
V
9
A
1
V
SS  
A
CC  
2
I/O  
49 I/O  
A
15  
8
3
I/O –I/O  
1M x 16  
ARRAY  
0
7
A
48  
47  
A
5
A
A
A
A
A
BHE  
4
7
4
3
A
5
A
8
6
I/O –I/O  
8
15  
A
6
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
A
7
9
2
A
7
A
10  
11  
12  
8
A
9
1
0
A
8
A
9
NC  
CE 13  
OE  
V
V
COLUMN  
DECODER  
CC  
SS  
14  
15  
16  
17  
18  
19  
20  
21  
22  
DNU/V  
BLE  
WE  
CC  
SS  
DNU/V  
A
19  
A
10  
A
18  
A
11  
BHE  
WE  
A
A
A
A
13  
17  
16  
15  
12  
A
A
14  
CE  
I/O  
V
I/O  
V
OE  
BLE  
0
7
23  
24  
25  
26  
27  
CC  
SS  
I/O  
I/O  
6
5
1
2
I/O  
I/O  
V
V
CC  
SS  
I/O  
28 I/O  
3
4
Notes:  
1. DNU/V Pin (#16) has to be left floating or connected to V and DNU/V Pin (#40) has to be left floating or connected to V to ensure proper application.  
CC  
CC  
SS  
SS  
2. NC – No Connect Pins are not connected to the die  
Cypress Semiconductor Corporation  
Document #: 38-05693 Rev. *B  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 3, 2006  
[+] Feedback  
1234567...9

中文翻译

下载PDF

与CY7C1061BV33-12ZXC相关器件

型号 品牌 获取价格 描述 数据表
CY7C1061BV33-12ZXCT CYPRESS

获取价格

 		Standard SRAM, 1MX16, 12ns, CMOS, PDSO54, LEAD FREE, TSOP2-54
CY7C1061BV33-12ZXI CYPRESS

获取价格

 		16-Mbit (1M x 16) Static RAM
CY7C1061BV33-12ZXIT CYPRESS

获取价格

 		暂无描述
CY7C1061DV33 CYPRESS

获取价格

 		16-Mbit (1M x 16) Static RAM
CY7C1061DV33_07 CYPRESS

获取价格

 		16-Mbit (1M x 16) Static RAM
CY7C1061DV33-10BAXI CYPRESS

获取价格

 		Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, FBGA-48
CY7C1061DV33-10BV1XI CYPRESS

获取价格

 		Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1061DV33-10BV1XIT CYPRESS

获取价格

 		Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1061DV33-10BVJXI CYPRESS

获取价格

 		Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48
CY7C1061DV33-10BVJXIT CYPRESS

获取价格

 		Standard SRAM, 1MX16, 10ns, CMOS, PBGA48, 8 X 9.50 MM, 1 MM HEIGHT, LEAD FREE, VFBGA-48

与CY7C1061BV33-12ZXC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证