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CY7C1061DV33

更新时间： 2024-11-19 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 407K
描述
16-Mbit (1M x 16) Static RAM

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CY7C1061DV33 数据手册

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CY7C1061DV33  
PRELIMINARY  
16-Mbit (1M x 16) Static RAM  
Features  
Functional Description  
• High speed  
The CY7C1061DV33 is a high-performance CMOS Static  
RAM organized as 1,048,576 words by 16 bits.  
— tAA = 10 ns  
Writing to the device is accomplished by enabling the chip  
(CE1 LOW and CE2 HIGH) while forcing the Write Enable  
(WE) input LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7), is written into the location  
specified on the address pins (A0 through A19). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A19).  
• Low active power  
— ICC = 125 mA @ 10 ns  
• Low CMOS standby power  
— ISB2 = 25 mA  
• Operating voltages of 3.3 ± 0.3V  
• 2.0V data retention  
Reading from the device is accomplished by enabling the chip  
by taking CE1 LOW and CE2 HIGH while forcing the Output  
Enable (OE) LOW and the Write Enable (WE) HIGH. If Byte  
Low Enable (BLE) is LOW, then data from the memory location  
specified by the address pins will appear on I/O0 to I/O7. If Byte  
High Enable (BHE) is LOW, then data from memory will appear  
on I/O8 to I/O15. See the truth table at the back of this data  
sheet for a complete description of Read and Write modes.  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE1 and CE2 features  
• Available in Pb-free 54-pin TSOP II package and 48-ball  
VFBGA packages  
The input/output pins (I/O0 through I/O15) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH/CE2 LOW), the outputs are disabled (OE HIGH), the  
BHE and BLE are disabled (BHE, BLE HIGH), or during a  
Write operation (CE1 LOW, CE2 HIGH, and WE LOW).  
The CY7C1061DV33 is available in a 54-pin TSOP II package  
with center power and ground (revolutionary) pinout, and a  
48-ball Very fine-pitch ball grid array (VFBGA) package  
Logic Block Diagram  
Pin Configuration  
54-pin TSOP II (Top View)  
I/O  
V
I/O  
I/O  
1
54  
53  
I/O  
V
11  
12  
CC  
INPUT BUFFER  
2
3
4
5
6
SS  
I/O  
52  
51  
50  
13  
14  
10  
A
0
I/O  
V
9
A
1
V
SS  
CC  
A
2
I/O  
49 I/O  
15  
8
A
4
3
A
A
3
48  
47  
A
5
I/O0–I/O7  
7
1M x 16  
ARRAY  
4
A
A
8
6
A
5
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
A
A
7
9
I/O8–I/O15  
2
A
6
A
10  
11  
12  
A
1
8
A
7
A
A
9
0
A
8
NC  
BHE  
CE1 13  
CC  
14  
A
9
OE  
V
V
SS  
WE  
NC  
15  
COLUMN  
DECODER  
CE2  
BLE  
16  
A
19  
A
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
10  
A
18  
A
11  
A
A
13  
17  
12  
A
A
16  
A
A
14  
15  
BHE  
WE  
I/O  
I/O  
0
7
CE2  
CE1  
V
V
CC  
SS  
I/O  
I/O  
6
5
1
2
OE  
BLE  
I/O  
V
I/O  
V
SS  
CC  
28 I/O  
I/O  
3
4
Cypress Semiconductor Corporation  
Document #: 38-05476 Rev. *C  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 14, 2006  
[+] Feedback  
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