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CY7C1041V33-17VCT PDF预览

CY7C1041V33-17VCT

更新时间: 2024-01-26 20:03:38
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
10页 180K
描述
Standard SRAM, 256KX16, 17ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, SOJ-44

CY7C1041V33-17VCT 技术参数

生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ,针数:44
Reach Compliance Code:unknownECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.6
最长访问时间:17 ns其他特性:AUTOMATIC POWER DOWN
JESD-30 代码:R-PDSO-J44内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
功能数量:1端子数量:44
字数:262144 words字数代码:256000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:256KX16
封装主体材料:PLASTIC/EPOXY封装代码:SOJ
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL认证状态:Not Qualified
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子位置:DUAL
Base Number Matches:1

CY7C1041V33-17VCT 数据手册

 浏览型号CY7C1041V33-17VCT的Datasheet PDF文件第2页浏览型号CY7C1041V33-17VCT的Datasheet PDF文件第3页浏览型号CY7C1041V33-17VCT的Datasheet PDF文件第4页浏览型号CY7C1041V33-17VCT的Datasheet PDF文件第5页浏览型号CY7C1041V33-17VCT的Datasheet PDF文件第6页浏览型号CY7C1041V33-17VCT的Datasheet PDF文件第7页 
V33  
CY7C1041V33  
256K x 16 Static RAM  
written into the location specified on the address pins (A  
Features  
0
through A ). If Byte High Enable (BHE) is LOW, then data  
17  
• High speed  
from I/O pins (I/O through I/O ) is written into the location  
8
15  
specified on the address pins (A through A ).  
0
17  
— t = 15 ns  
AA  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O to I/O . If Byte High Enable (BHE) is  
• Low active power  
— 612 mW (max.)  
• Low CMOS standby power (Commercial L version)  
— 1.8 mW (max.)  
0
7
LOW, then data from memory will appear on I/O to I/O . See  
8
15  
• 2.0V Data Retention (600 W at 2.0V retention)  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
µ
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
The input/output pins (I/O through I/O ) are placed in a  
0
15  
• Easy memory expansion with CE and OE features  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
Functional Description  
The CY7C1041V33 is a high-performance CMOS Static RAM  
organized as 262,144 words by 16 bits.  
The CY7C1041V33 is available in  
a standard 44-pin  
400-mil-wide body width SOJ and 44-pin TSOP II package  
with center power and ground (revolutionary) pinout.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
0
7
Logic Block Diagram  
Pin Configuration  
SOJ  
TSOP II  
Top View  
INPUT BUFFER  
A
44  
1
0
A
A
A
A
OE  
BHE  
BLE  
I/O  
I/O  
I/O  
0
17  
16  
15  
A
43  
42  
41  
40  
39  
38  
1
A
2
3
4
5
6
1
A
2
A
2
I/O0 – I/O7  
I/O8 – I/O15  
256K x 16  
ARRAY  
A
3
4
A
3
A
A
4
1024 x 4096  
A
5
6
CE  
A
I/O  
7
0
15  
A
7
8
37  
36  
35  
34  
33  
I/O  
I/O  
8
1
2
14  
13  
12  
A
9
10  
11  
12  
13  
I/O  
V
SS  
I/O  
3
CC  
V
SS  
COLUMN  
DECODER  
V
V
CC  
I/O  
32  
I/O  
I/O  
4
5
6
7
11  
10  
I/O  
I/O  
I/O  
31  
30  
29  
28  
14  
15  
16  
I/O  
I/O  
NC  
9
8
WE 17  
BHE  
18  
27  
26  
25  
A
14  
A
WE  
CE  
OE  
5
19  
A
6
A
13  
A
20  
21  
22  
A
7
12  
A
BLE  
A
24  
23  
11  
8
9
A
A
10  
1041V33–1  
1041V33–2  
Selection Guide  
1041V33-12 1041V33-15 1041V33-17 1041V33-20 1041V33-25  
Maximum Access Time (ns)  
12  
190  
8
15  
170  
8
17  
160  
8
20  
150  
8
25  
130  
8
Maximum Operating Current (mA)  
Maximum CMOS Standby Current (mA) Com’l/Ind’l  
Com’l  
L
0.5  
0.5  
0.5  
0.5  
0.5  
Shaded areas contain preliminary information.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
June 2, 1999  

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