5秒后页面跳转
捷配首页

Datasheet > CY7C1041CV33-12BAIT
CY7C1041CV33-12BAIT PDF预览

CY7C1041CV33-12BAIT

更新时间： 2024-11-02 21:06:59
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
12页 253K
描述
Standard SRAM, 256KX16, 12ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, FBGA-48

阅读下载

中文翻译

获取价格

CY7C1041CV33-12BAIT 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：FBGA,针数：48
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.6
最长访问时间：12 nsJESD-30 代码：R-PBGA-B48
长度：8.5 mm内存密度：4194304 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
功能数量：1端子数量：48
字数：262144 words字数代码：256000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX16
封装主体材料：PLASTIC/EPOXY封装代码：FBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, FINE PITCH
并行/串行：PARALLEL认证状态：Not Qualified
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM宽度：7 mm
Base Number Matches：1

CY7C1041CV33-12BAIT 数据手册

 浏览型号CY7C1041CV33-12BAIT的Datasheet PDF文件第2页浏览型号CY7C1041CV33-12BAIT的Datasheet PDF文件第3页浏览型号CY7C1041CV33-12BAIT的Datasheet PDF文件第4页浏览型号CY7C1041CV33-12BAIT的Datasheet PDF文件第5页浏览型号CY7C1041CV33-12BAIT的Datasheet PDF文件第6页浏览型号CY7C1041CV33-12BAIT的Datasheet PDF文件第7页 
CY7C1041CV33  
4-Mbit (256K x 16) Static RAM  
Features  
Functional Description[1]  
• Pin equivalent to CY7C1041BV33  
• Temperature Ranges  
The CY7C1041CV33 is a high-performance CMOS Static  
RAM organized as 262,144 words by 16 bits.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable  
(BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written  
into the location specified on the address pins (A0–A17). If Byte  
HIGH Enable (BHE) is LOW, then data from I/O pins  
(I/O8–I/O15) is written into the location specified on the  
address pins (A0–A17).  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• High speed  
— tAA = 10 ns  
• Low active power  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of Read and Write modes.  
— 324 mW (max.)  
• 2.0V data retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
The input/output pins (I/O0–I/O15  
)
are placed in  
a
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a Write operation  
(CE LOW, and WE LOW).  
The CY7C1041CV33 is available in a standard 44-pin  
400-mil-wide body width SOJ and 44-pin TSOP II package  
with center power and ground (revolutionary) pinout, as well  
as a 48-ball fine-pitch ball grid array (FBGA) package.  
Logic Block Diagram  
Pin Configuration  
SOJ  
TSOP II  
Top View  
INPUT BUFFER  
44  
43  
42  
41  
40  
39  
38  
1
2
3
4
5
6
A
A
17  
0
A
A
16  
A
0
1
A
A
15  
A
1
2
A
2
A
OE  
BHE  
BLE  
3
I/O –I/O  
256K × 16  
0
7
A
A
3
4
ARRAY  
A
4
CE  
1024 x 4096  
I/O –I/O  
A
I/O  
I/O  
5
7
8
15  
0
15  
A
6
37  
36  
35  
34  
33  
32  
I/O  
I/O  
8
I/O  
I/O  
1
2
14  
13  
12  
A
7
9
A
8
10  
11  
12  
13  
I/O  
V
SS  
I/O  
3
CC  
V
SS  
V
V
CC  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
COLUMN  
DECODER  
31  
30  
29  
28  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
9
8
I/O  
WE 17  
NC  
18  
27  
26  
25  
A
14  
A
5
BHE  
WE  
CE  
OE  
BLE  
19  
A
A
6
13  
A
20  
21  
22  
A
7
12  
A
11  
A
24  
23  
8
9
A
A
10  
Notes:  
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05134 Rev. *F  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised April 29, 2004  
1234567...12

中文翻译

下载PDF

与CY7C1041CV33-12BAIT相关器件

型号 品牌 获取价格 描述 数据表
CY7C1041CV33-12BAXE CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY7C1041CV33-12BAXET CYPRESS

获取价格

 		Standard SRAM, 256KX16, CMOS, PBGA48
CY7C1041CV33-12VC CYPRESS

获取价格

 		256K x 16 Static RAM
CY7C1041CV33-12VC ROCHESTER

获取价格

 		256KX16 STANDARD SRAM, 12ns, PDSO44, 0.400 INCH, SOJ-44
CY7C1041CV33-12VI CYPRESS

获取价格

 		256K x 16 Static RAM
CY7C1041CV33-12VXC CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY7C1041CV33-12VXI CYPRESS

获取价格

 		4-Mbit (256K x 16) Static RAM
CY7C1041CV33-12ZC CYPRESS

获取价格

 		256K x 16 Static RAM
CY7C1041CV33-12ZCT ROCHESTER

获取价格

 		Standard SRAM, 256KX16, 12ns, CMOS, PDSO44, TSOP2-44
CY7C1041CV33-12ZI CYPRESS

获取价格

 		256K x 16 Static RAM

与CY7C1041CV33-12BAIT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证