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CY7C1041CV33-10BAXI PDF预览

CY7C1041CV33-10BAXI

更新时间： 2024-11-02 05:19:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 599K
描述
4-Mbit (256K x 16) Static RAM

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CY7C1041CV33-10BAXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：BGA包装说明：7 X 8.50 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-48
针数：48Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.58
最长访问时间：10 nsI/O 类型：COMMON
JESD-30 代码：R-PBGA-B48JESD-609代码：e1
长度：8.5 mm内存密度：4194304 bit
内存集成电路类型：STANDARD SRAM内存宽度：16
湿度敏感等级：3功能数量：1
端子数量：48字数：262144 words
字数代码：256000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：256KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装等效代码：BGA48,6X8,30封装形状：RECTANGULAR
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行：PARALLEL
峰值回流温度（摄氏度）：260电源：3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
最大待机电流：0.01 A最小待机电流：3 V
子类别：SRAMs最大压摆率：0.1 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：3 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：7 mm
Base Number Matches：1

CY7C1041CV33-10BAXI 数据手册

 浏览型号CY7C1041CV33-10BAXI的Datasheet PDF文件第2页浏览型号CY7C1041CV33-10BAXI的Datasheet PDF文件第3页浏览型号CY7C1041CV33-10BAXI的Datasheet PDF文件第4页浏览型号CY7C1041CV33-10BAXI的Datasheet PDF文件第5页浏览型号CY7C1041CV33-10BAXI的Datasheet PDF文件第6页浏览型号CY7C1041CV33-10BAXI的Datasheet PDF文件第7页 
CY7C1041CV33  
4-Mbit (256K x 16) Static RAM  
Features  
Functional Description[1]  
• Pin equivalent to CY7C1041BV33  
• Temperature Ranges  
The CY7C1041CV33 is a high-performance CMOS Static  
RAM organized as 262,144 words by 16 bits.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable  
(BLE) is LOW, then data from I/O pins (I/O0–I/O7), is written  
into the location specified on the address pins (A0–A17). If Byte  
HIGH Enable (BHE) is LOW, then data from I/O pins  
(I/O8–I/O15) is written into the location specified on the  
address pins (A0–A17).  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• High speed  
— tAA = 10 ns  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 – I/O7. If Byte HIGH Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of Read and Write modes.  
• Low active power  
— 324 mW (max.)  
• 2.0V data retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
The input/output pins (I/O0–I/O15  
)
are placed in  
a
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a Write operation  
(CE LOW, and WE LOW).  
• Available in Pb-free and non Pb-free 44-pin 400-mil-  
SOJ, 44-pin TSOP II and 48-ball FBGA packages  
The CY7C1041CV33 is available in a standard 44-pin  
400-mil-wide body width SOJ and 44-pin TSOP II package  
with center power and ground (revolutionary) pinout, as well  
as a 48-ball fine-pitch ball grid array (FBGA) package.  
Logic Block Diagram  
Pin Configuration  
SOJ/  
TSOP II  
Top View  
INPUT BUFFER  
44  
43  
42  
41  
40  
39  
38  
1
2
3
4
5
6
A
A
17  
0
A
A
16  
A
0
1
A
A
15  
A
1
2
A
2
A
OE  
BHE  
BLE  
3
I/O –I/O  
256K × 16  
0
7
A
A
3
4
ARRAY  
A
4
CE  
I/O –I/O  
A
I/O  
I/O  
5
7
8
15  
0
15  
A
6
37  
36  
35  
34  
33  
32  
I/O  
I/O  
8
I/O  
I/O  
1
2
14  
13  
12  
A
7
9
A
8
10  
11  
12  
13  
I/O  
V
SS  
I/O  
3
CC  
V
SS  
V
V
CC  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
COLUMN  
DECODER  
31  
30  
29  
28  
I/O  
I/O  
I/O  
14  
15  
16  
I/O  
9
8
I/O  
WE 17  
NC  
18  
27  
26  
25  
A
14  
A
5
BHE  
WE  
CE  
OE  
BLE  
19  
A
A
6
13  
A
20  
21  
22  
A
7
12  
A
11  
A
24  
23  
8
9
A
A
10  
Notes:  
1. For guidelines on SRAM system design, please refer to the “System Design Guidelines” Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05134 Rev. *H  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised September 1, 2006  
[+] Feedback  
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中文翻译

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CY7C1041CV33-10BAXI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1041CV33-10BAI CYPRESS

完全替代

 256K x 16 Static RAM
CY7C1041CV33-10BAC CYPRESS

完全替代

 256K x 16 Static RAM
CY7C1041CV33-10BAXIT CYPRESS

类似代替

 Standard SRAM, 256KX16, 10ns, CMOS, PBGA48, 7 X 8.50 MM, 1.20 MM HEIGHT, LEAD FREE, FBGA-4

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