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CY7C1041CV33-10ZI PDF预览

CY7C1041CV33-10ZI

更新时间: 2024-02-17 19:10:40
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 229K
描述
256K x 16 Static RAM

CY7C1041CV33-10ZI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:LEAD FREE, TSOP2-44
针数:44Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.29最长访问时间:10 ns
JESD-30 代码:R-PDSO-G44JESD-609代码:e4
长度:18.415 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:44字数:262144 words
字数代码:256000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:256KX16封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1.194 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
宽度:10.16 mm

CY7C1041CV33-10ZI 数据手册

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CY7C1041CV33  
256K x 16 Static RAM  
HIGH Enable (BHE) is LOW, then data from I/O pins  
(I/O8I/O15) is written into the location specified on the  
address pins (A0A17).  
Features  
• Pin equivalent to CY7C1041BV33  
• High speed  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte LOW Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 I/O7. If Byte HIGH Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of Read and Write modes.  
— tAA = 10 ns  
• Low active power  
— 324 mW (max.)  
• 2.0V data retention  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
• Easy memory expansion with CE and OE features  
The input/output pins (I/O0I/O15  
)
are placed in  
a
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a Write operation  
(CE LOW, and WE LOW).  
Functional Description[1]  
The CY7C1041CV33 is a high-performance CMOS Static  
RAM organized as 262,144 words by 16 bits.  
The CY7C1041CV33 is available in a standard 44-pin  
400-mil-wide body width SOJ and 44-pin TSOP II package  
with center power and ground (revolutionary) pinout, as well  
as a 48-ball fine-pitch ball grid array (FBGA) package.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte LOW Enable  
(BLE) is LOW, then data from I/O pins (I/O0I/O7), is written  
into the location specified on the address pins (A0A17). If Byte  
Logic Block Diagram  
Pin Configuration  
SOJ  
TSOP II  
Top View  
INPUT BUFFER  
44  
1
A
A
A
A
OE  
BHE  
BLE  
0
17  
16  
15  
A
0
A
1
43  
42  
41  
40  
39  
38  
A
2
3
4
5
6
1
A
2
A
2
A
3
I/O I/O  
256K × 16  
ARRAY  
0
7
A
3
4
A
4
A
CE  
1024 x 4096  
A
I/O I/O  
8 15  
5
6
I/O  
I/O  
7
0
15  
A
37  
36  
35  
34  
33  
I/O  
I/O  
8
I/O  
I/O  
1
2
14  
13  
12  
A
8
7
9
A
10  
11  
12  
13  
I/O  
V
SS  
I/O  
3
CC  
V
SS  
V
V
CC  
COLUMN  
DECODER  
32  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
I/O  
I/O  
I/O  
31  
30  
29  
28  
14  
15  
16  
I/O  
9
8
I/O  
WE 17  
18  
NC  
27  
26  
25  
BHE  
WE  
CE  
OE  
BLE  
A
14  
A
5
19  
20  
21  
22  
A
A
13  
A
12  
A
11  
6
A
7
A
24  
23  
8
9
A
A
10  
Selection Guide  
-8  
-10  
10  
-12  
12  
85  
95  
10  
-15  
15  
80  
90  
10  
-20  
20  
75  
85  
10  
Unit  
ns  
Maximum Access Time  
8
Maximum Operating Current  
Commercial  
Industrial  
100  
110  
10  
90  
mA  
mA  
mA  
100  
10  
Maximum CMOS Standby Current  
Commercial/  
Industrial  
Shaded areas contain advance information.  
Note:  
1. For guidelines on SRAM system design, please refer to the System Design GuidelinesCypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05134 Rev. *D  
Revised October 18, 2002  

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