CY7C1020B
32K x 16 Static RAM
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is
written into the location specified on the address pins (A0
through A14). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O9 through I/O16) is written into the location
specified on the address pins (A0 through A14).
Features
• High speed
— tAA = 12, 15 ns
• CMOS for optimum speed/power
• Low active power
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O9 to I/O16. See
the truth table at the back of this data sheet for a complete
description of read and write modes.
— 825 mW (max.)
• Low CMOS standby power
— 16.5 mW (max.)
• Automatic power-down when deselected
• Independent control of upper and lower bits
• Available in lead-free and non-lead-free 44-pin TSOP II
and 44-pin (400-mil) SOJ packages
The input/output pins (I/O1 through I/O16) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE
are disabled (BHE, BLE HIGH), or during a write operation (CE
LOW, and WE LOW).
Functional Description
The CY7C1020B is a high-performance CMOS static RAM
organized as 32,768 words by 16 bits. This device has an
automatic power-down feature that significantly reduces
power consumption when deselected.
The CY7C1020B is available in standard 44-pin TSOP Type II
and 44-pin 400-mil-wide SOJ packages.
Logic Block Diagram
Pin Configuration
SOJ / TSOP II Pinout
DATA IN DRIVERS
Top View
44
1
NC
A
5
43
42
41
40
39
38
A
A
2
3
4
5
6
3
6
A
A
2
7
A7
A6
OE
A
1
BHE
BLE
I/O
I/O
I/O
A
0
A5
A4
A3
A2
A1
32K x 16
CE
I/O1–I/O8
RAM Array
I/O
7
1
16
37
36
35
34
33
I/O
I/O
8
2
3
15
14
13
I/O9–I/O16
9
10
11
12
13
I/O
V
SS
I/O
4
CC
V
SS
A0
V
V
CC
32
31
30
29
28
I/O
I/O
I/O
5
6
7
8
12
11
I/O
I/O
I/O
14
15
16
I/O
I/O
10
9
COLUMN DECODER
WE 17
NC
18
27
26
25
A
A
8
4
BHE
19
A
13
A
14
9
WE
CE
OE
A
20
21
22
A
11
10
A
A
12
24
23
NC
NC
BLE
Selection Guide
CY7C1020B-12
CY7C1020B-15
Maximum Access Time (ns)
12
140
3
15
130
3
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
Cypress Semiconductor Corporation
Document #: 38-05171 Rev. *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 26, 2006
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