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CY7C1019B-15ZXCT PDF预览

CY7C1019B-15ZXCT

更新时间: 2024-10-28 20:05:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
8页 319K
描述
Standard SRAM, 128KX8, 15ns, CMOS, PDSO32, LEAD FREE, TSOP2-32

CY7C1019B-15ZXCT 技术参数

生命周期:Obsolete零件包装代码:TSOP2
包装说明:LEAD FREE, TSOP2-32针数:32
Reach Compliance Code:unknownECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.34
最长访问时间:15 nsJESD-30 代码:R-PDSO-G32
JESD-609代码:e3长度:20.95 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:8功能数量:1
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX8封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1.2 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
宽度:10.16 mmBase Number Matches:1

CY7C1019B-15ZXCT 数据手册

 浏览型号CY7C1019B-15ZXCT的Datasheet PDF文件第1页浏览型号CY7C1019B-15ZXCT的Datasheet PDF文件第2页浏览型号CY7C1019B-15ZXCT的Datasheet PDF文件第4页浏览型号CY7C1019B-15ZXCT的Datasheet PDF文件第5页浏览型号CY7C1019B-15ZXCT的Datasheet PDF文件第6页浏览型号CY7C1019B-15ZXCT的Datasheet PDF文件第7页 
CY7C1019B  
Switching Characteristics[4] Over the Operating Range  
-12  
-15  
Parameter  
Description  
Min.  
12  
3
Max.  
Min.  
15  
3
Max.  
Unit  
Read Cycle  
tRC  
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
Address to Data Valid  
12  
15  
tOHA  
Data Hold from Address Change  
tACE  
LOW to Data Valid  
LOW to Data Valid  
LOW to Low Z  
HIGH to High Z[5, 6]  
LOW to Low Z[6]  
HIGH to High Z[5, 6]  
LOW to Power-Up  
HIGH to Power-Down  
12  
6
15  
7
CE  
OE  
OE  
OE  
CE  
CE  
CE  
CE  
tDOE  
tLZOE  
tHZOE  
tLZCE  
tHZCE  
tPU  
0
3
0
0
3
0
6
6
7
7
tPD  
12  
15  
Write Cycle[7, 8]  
tWC  
Write Cycle Time  
LOW to Write End  
12  
9
15  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tSCE  
CE  
tAW  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
8
tHA  
0
tSA  
0
0
tPWE  
tSD  
Pulse Width  
8
10  
8
WE  
Data Set-Up to Write End  
6
tHD  
Data Hold from Write End  
HIGH to Low Z[6]  
WE  
0
0
tLZWE  
tHZWE  
3
3
LOW to High Z[5, 6]  
6
7
WE  
Notes:  
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
I
/I and 30-pF load capacitance.  
OL OH  
5. t  
, t  
, and t  
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
HZOE HZCE  
HZWE  
6. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given device.  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
LZWE  
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any  
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.  
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t  
and t  
.
SD  
HZWE  
Document #: 38-05026 Rev. *C  
Page 3 of 8  

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