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CY7C1018DV33-10VXI PDF预览

CY7C1018DV33-10VXI

更新时间： 2024-11-05 05:09:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 267K
描述
1-Mbit (128K x 8) Static RAM

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CY7C1018DV33-10VXI 数据手册

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CY7C1018DV33  
1-Mbit (128K x 8) Static RAM  
Features  
Functional Description[1]  
• Pin- and function-compatible with CY7C1018CV33  
• High speed  
The CY7C1018DV33 is a high-performance CMOS static  
RAM organized as 131,072 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and tri-state drivers. This  
device has an automatic power-down feature that significantly  
reduces power consumption when deselected.  
— tAA = 10 ns  
• Low Active Power  
— ICC = 60 mA @ 10 ns  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O0 through I/O7) is then written into the location  
specified on the address pins (A0 through A16).  
• Low CMOS Standby Power  
— ISB2 = 3 mA  
• 2.0V Data retention  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
• Center power/ground pinout  
• Easy memory expansion with CE and OE options  
• Available in Pb-free 32-pin 300-Mil wide Molded SOJ  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
The CY7C1018DV33 is available in Pb-free 32-pin 300-Mil  
wide Molded SOJ.  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
A
A
1
A
A
32  
31  
30  
1
0
16  
2
3
4
5
6
15  
A
2
A
14  
A
13  
A
29  
28  
3
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
CE  
INPUTBUFFER  
OE  
I/O  
I/O  
27  
26  
I/O  
0
1
7
A
0
I/O  
V
7
8
9
10  
11  
12  
13  
6
A
1
25  
24  
23  
22  
21  
V
CC  
SS  
A
2
V
V
CC  
I/O  
SS  
A
3
128K × 8  
ARRAY  
I/O  
I/O  
A
2
3
4
5
4
A
5
I/O  
A
A
6
WE  
A
4
12  
A
7
A
11  
20  
19  
A
8
A
5
A
10  
14  
15  
16  
A
6
A
9
A
8
18  
17  
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
A
7
I/O  
7
OE  
Note  
1. For guidelines on SRAM system designs, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05465 Rev. *D  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised November 8, 2006  
[+] Feedback  
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CY7C1018DV33-10VXI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C1018CV33-12VXI CYPRESS

类似代替

 128K x 8 Static RAM
IS63LV1024L-12JL ISSI

功能相似

 128K x 8 HIGH-SPEED CMOS STATIC RAM 3.3V REVOLUTIONARY PINOUT

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