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CY7C1019-10VC PDF预览

CY7C1019-10VC

更新时间: 2024-11-06 09:43:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
8页 158K
描述
128K x 8 Static RAM

CY7C1019-10VC 技术参数

生命周期:Obsolete零件包装代码:SOJ
包装说明:SOJ, SOJ32,.44针数:32
Reach Compliance Code:compliantECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.68
最长访问时间:10 ns其他特性:AUTOMATIC POWER-DOWN
I/O 类型:COMMONJESD-30 代码:R-PDSO-J32
长度:20.955 mm内存密度:1048576 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
功能数量:1端口数量:1
端子数量:32字数:131072 words
字数代码:128000工作模式:ASYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:128KX8输出特性:3-STATE
可输出:YES封装主体材料:PLASTIC/EPOXY
封装代码:SOJ封装等效代码:SOJ32,.44
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
并行/串行:PARALLEL电源:5 V
认证状态:Not Qualified座面最大高度:3.7592 mm
最大待机电流:0.01 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.24 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:J BEND端子节距:1.27 mm
端子位置:DUAL宽度:10.16 mm

CY7C1019-10VC 数据手册

 浏览型号CY7C1019-10VC的Datasheet PDF文件第2页浏览型号CY7C1019-10VC的Datasheet PDF文件第3页浏览型号CY7C1019-10VC的Datasheet PDF文件第4页浏览型号CY7C1019-10VC的Datasheet PDF文件第5页浏览型号CY7C1019-10VC的Datasheet PDF文件第6页浏览型号CY7C1019-10VC的Datasheet PDF文件第7页 
019  
PRELIMINARY  
CY7C1019  
128K x 8 Static RAM  
Writing to the device is accomplished by taking chip enable  
(CE) and write enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O0 through I/O7) is then written into the location speci-  
fied on the address pins (A0 through A16).  
Features  
• High speed  
— tAA = 10 ns  
Reading from the device is accomplished by taking chip en-  
able (CE) and output enable (OE) LOW while forcing write  
enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• CMOS for optimum speed/power  
• Center power/ground pinout  
• Automatic power-down when deselected  
• Easy memory expansion with CE and OE options  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Functional Description  
The CY7C1019 is a high-performance CMOS static RAM or-  
ganized as 131,072 words by 8 bits. Easy memory expansion  
is provided by an active LOW chip enable (CE), an active LOW  
output enable (OE), and three-state drivers. This device has  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
The CY7C1019 is available in standard 400-mil-wide SOJs.  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
A
A
1
A
A
32  
1
0
16  
31  
30  
2
3
4
5
6
15  
A
2
A
A
14  
A
3
29  
28  
13  
I/O  
0
CE  
OE  
I/O  
27  
26  
INPUT BUFFER  
I/O  
0
7
I/O  
V
I/O  
V
7
8
9
10  
11  
12  
13  
1
6
I/O  
1
I/O  
2
25  
24  
23  
22  
21  
CC  
SS  
A
0
V
V
CC  
I/O  
SS  
A
1
I/O  
I/O  
2
3
5
4
A
2
I/O  
A
A
3
4
WE  
A
4
12  
11  
A
A
A
I/O  
3
I/O  
4
I/O  
5
20  
19  
512 x 256 x 8  
ARRAY  
A
6
A
5
5
10  
14  
15  
16  
A
A
6
A
A
18  
17  
9
A
A
7
8
7
8
A
10192  
I/O  
6
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
7
WE  
10191  
OE  
Selection Guide  
7C1019–10  
7C1019–12  
7C1019–15  
Maximum Access Time (ns)  
10  
240  
210  
10  
12  
220  
190  
10  
15  
200  
175  
10  
Maximum Operating Current (mA)  
L
L
Maximum Standby Current (mA)  
1
1
1
Shaded areas contain advance information.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-05055 Rev. **  
Revised August 31, 2001  

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