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CY7C1019

更新时间： 2024-11-27 09:43:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
8页 158K
描述
128K x 8 Static RAM

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中文翻译

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CY7C1019 数据手册

 浏览型号CY7C1019的Datasheet PDF文件第2页浏览型号CY7C1019的Datasheet PDF文件第3页浏览型号CY7C1019的Datasheet PDF文件第4页浏览型号CY7C1019的Datasheet PDF文件第5页浏览型号CY7C1019的Datasheet PDF文件第6页浏览型号CY7C1019的Datasheet PDF文件第7页 
019  
PRELIMINARY  
CY7C1019  
128K x 8 Static RAM  
Writing to the device is accomplished by taking chip enable  
(CE) and write enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O0 through I/O7) is then written into the location speci-  
fied on the address pins (A0 through A16).  
Features  
• High speed  
— tAA = 10 ns  
Reading from the device is accomplished by taking chip en-  
able (CE) and output enable (OE) LOW while forcing write  
enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• CMOS for optimum speed/power  
• Center power/ground pinout  
• Automatic power-down when deselected  
• Easy memory expansion with CE and OE options  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Functional Description  
The CY7C1019 is a high-performance CMOS static RAM or-  
ganized as 131,072 words by 8 bits. Easy memory expansion  
is provided by an active LOW chip enable (CE), an active LOW  
output enable (OE), and three-state drivers. This device has  
an automatic power-down feature that significantly reduces  
power consumption when deselected.  
The CY7C1019 is available in standard 400-mil-wide SOJs.  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
A
A
1
A
A
32  
1
0
16  
31  
30  
2
3
4
5
6
15  
A
2
A
A
14  
A
3
29  
28  
13  
I/O  
0
CE  
OE  
I/O  
27  
26  
INPUT BUFFER  
I/O  
0
7
I/O  
V
I/O  
V
7
8
9
10  
11  
12  
13  
1
6
I/O  
1
I/O  
2
25  
24  
23  
22  
21  
CC  
SS  
A
0
V
V
CC  
I/O  
SS  
A
1
I/O  
I/O  
2
3
5
4
A
2
I/O  
A
A
3
4
WE  
A
4
12  
11  
A
A
A
I/O  
3
I/O  
4
I/O  
5
20  
19  
512 x 256 x 8  
ARRAY  
A
6
A
5
5
10  
14  
15  
16  
A
A
6
A
A
18  
17  
9
A
A
7
8
7
8
A
1019–2  
I/O  
6
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
7
WE  
1019–1  
OE  
Selection Guide  
7C1019–10  
7C1019–12  
7C1019–15  
Maximum Access Time (ns)  
10  
240  
210  
10  
12  
220  
190  
10  
15  
200  
175  
10  
Maximum Operating Current (mA)  
L
L
Maximum Standby Current (mA)  
1
1
1
Shaded areas contain advance information.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05055 Rev. **  
Revised August 31, 2001  
12345678

中文翻译

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