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CY7C1019B-10VI

更新时间： 2024-11-23 22:09:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 197K
描述
128K x 8 Static RAM

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中文翻译

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CY7C1019B-10VI 数据手册

 浏览型号CY7C1019B-10VI的Datasheet PDF文件第2页浏览型号CY7C1019B-10VI的Datasheet PDF文件第3页浏览型号CY7C1019B-10VI的Datasheet PDF文件第4页浏览型号CY7C1019B-10VI的Datasheet PDF文件第5页浏览型号CY7C1019B-10VI的Datasheet PDF文件第6页浏览型号CY7C1019B-10VI的Datasheet PDF文件第7页 
C1019V33  
CY7C1019B/  
CY7C10191B  
128K x 8 Static RAM  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O0 through I/O7) is then written into the location speci-  
fied on the address pins (A0 through A16).  
Features  
• High speed  
— tAA = 10, 12, 15 ns  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
• CMOS for optimum speed/power  
• Center power/ground pinout  
• Automatic power-down when deselected  
• Easy memory expansion with CE and OE options  
• Functionally equivalent to CY7C1019  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Functional Description  
The CY7C1019B/10191B is a high-performance CMOS static  
RAM organized as 131,072 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and three-state drivers. This  
device has an automatic power-down feature that significantly  
reduces power consumption when deselected.  
The CY7C1019B/10191B is available in standard 32-pin  
TSOP Type II and 400-mil-wide SOJ packages. Customers  
should use part number CY7C10191B when ordering parts  
with 10 ns tAA, and CY7C1019B when ordering 12 and 15 ns  
tAA  
.
ogic Block Diagram  
Pin Configurations  
/ TSOPII  
SOJ  
Top View  
A
A
1
A
16  
32  
31  
30  
1
0
A
15  
2
3
4
5
6
A
2
A
14  
A
A
13  
29  
28  
3
I/O  
0
INPUT BUFFER  
CE  
I/O  
OE  
I/O  
27  
26  
I/O  
I/O  
1
2
0
7
A
0
I/O  
I/O  
6
7
1
A
1
25  
24  
23  
22  
21  
V
V
A
8
9
10  
11  
12  
13  
V
V
CC  
I/O  
I/O  
4
CC  
2
SS  
A
3
4
SS  
A
I/O  
3
I/O  
4
I/O  
5
512 x 256 x 8  
ARRAY  
I/O  
2
I/O  
5
A
5
6
A
3
A
A
7
8
WE  
A
12  
A
A
11  
4
20  
19  
A
A
10  
5
14  
15  
16  
A
A
I/O  
6
18  
17  
9
6
7
POWER  
DOWN  
COLUMN  
DECODER  
A
8
A
CE  
7
I/O  
WE  
OE  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05026 Rev. *A  
Revised August 13, 2002  
1234567...9

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