07B
CY7C107B
CY7C1007B
1M x 1 Static RAM
Writing to the devices is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the input pin
(DIN) is written into the memory location specified on the ad-
dress pins (A0 through A19).
Features
• High speed
— tAA = 12 ns
Reading from the devices is accomplished by taking Chip En-
able (CE) LOW while Write Enable (WE) remains HIGH. Under
these conditions, the contents of the memory location speci-
• CMOS for optimum speed/power
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
fied by the address pins will appear on the data output (DOUT
)
pin.
Functional Description
The output pin (DOUT) is placed in a high-impedance state
when the device is deselected (CE HIGH) or during a write
operation (CE and WE LOW).
The CY7C107B and CY7C1007B are high-performance
CMOS static RAMs organized as 1,048,576 words by 1 bit.
Easy memory expansion is provided by an active LOW Chip
Enable (CE) and three-state drivers. These devices have an
automatic power-down feature that reduces power consump-
tion by more than 65% when deselected.
The CY7C107B is available in a standard 400-mil-wide SOJ;
the CY7C1007B is available in a standard 300-mil-wide SOJ.
Logic Block Diagram
Pin Configuration
SOJ
Top View
D
IN
28
27
26
1
2
3
4
5
6
A
A
A
A
A
A
V
CC
10
11
12
13
14
15
A
9
A
8
25
24
A
7
INPUT BUFFER
A
6
A
A0
23
22
5
A1
A2
A3
A4
A5
A6
A7
A8
7
8
9
10
11
12
13
NC
A
4
21
20
19
18
17
A
17
NC
16
A
A
3
A
19
A
2
18
512x2048
ARRAY
A
A
1
D
OUT
A
0
D
OUT
WE
GND
16
15
D
IN
14
CE
107B-2
POWER
DOWN
COLUMN
DECODER
CE
WE
107B-1
Selection Guide
7C107B-12
7C1007B-12
7C107B-15
7C1007B-15
7C107B-20
7C1007B-20
7C107B-25
7C1007B-25
7C107B-35
7C1007B-35
Maximum Access Time (ns)
12
90
15
80
20
75
25
70
35
60
Maximum Operating
Current (mA)
Maximum CMOS Standby
Current SB2 (mA)
2
2
2
2
2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-05030 Rev. **
Revised September 7, 2001