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CY7C09369A-7AC PDF预览

CY7C09369A-7AC

更新时间： 2024-01-16 01:37:28
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
18页 345K
描述
16K x16/18 Synchronous Dual Port Static RAM

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CY7C09369A-7AC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：PLASTIC, TQFP-100
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.83最长访问时间：18 ns
其他特性：FLOW-THROUGH OR PIPELINED ARCHITECTURE最大时钟频率 (fCLK)：83 MHz
I/O 类型：COMMONJESD-30 代码：S-PQFP-G100
JESD-609代码：e0长度：14 mm
内存密度：294912 bit内存集成电路类型：DUAL-PORT SRAM
内存宽度：18功能数量：1
端口数量：2端子数量：100
字数：16384 words字数代码：16000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：16KX18
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP100,.63SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：5 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.0005 A
最小待机电流：4.5 V子类别：SRAMs
最大压摆率：0.42 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

CY7C09369A-7AC 数据手册

 浏览型号CY7C09369A-7AC的Datasheet PDF文件第1页浏览型号CY7C09369A-7AC的Datasheet PDF文件第2页浏览型号CY7C09369A-7AC的Datasheet PDF文件第3页浏览型号CY7C09369A-7AC的Datasheet PDF文件第5页浏览型号CY7C09369A-7AC的Datasheet PDF文件第6页浏览型号CY7C09369A-7AC的Datasheet PDF文件第7页 
CY7C09269A  
CY7C09369A  
Pin Definitions  
Left Port  
A0L–A13L  
ADSL  
Right Port  
Description  
A0R–A13R  
Address Inputs.  
ADSR  
Address Strobe Input. Used as an address qualifier. This signal should be asserted LOW to  
access the part using an externally supplied address. Asserting this signal LOW also loads the  
burst counter with the address present on the address pins.  
CE0L,CE1L  
CE0R,CE1R  
Chip Enable Input. To select either the left or right port, both CE0 AND CE1 must be asserted  
to their active states (CE0 ≤ VIL and CE1 ≥ VIH).  
CLKL  
CLKR  
Clock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.  
CNTENL  
CNTENR  
Counter Enable Input. Asserting this signal LOW increments the burst address counter of its  
respective port on each rising edge of CLK. CNTEN is disabled if ADS or CNTRST are asserted  
LOW.  
CNTRSTL  
CNTRSTR  
Counter Reset Input. Asserting this signal LOW resets the burst address counter of its respec-  
tive port to zero. CNTRST is not disabled by asserting ADS or CNTEN.  
I/O0L–I/O17L  
I/O0R–I/O17R Data Bus Input/Output (I/O0–I/O15 for x16 devices).  
LBL  
LBR  
Lower Byte Select Input. Asserting this signal LOW enables read and write operations to the  
lower byte. (I/O0–I/O8 for x18, I/O0–I/O7 for x16) of the memory array. For read operations both  
the LB and OE signals must be asserted to drive output data on the lower byte of the data pins.  
UBL  
OEL  
UBR  
OER  
Upper Byte Select Input. Same function as LB, but to the upper byte (I/O8/9L–I/O15/17L).  
Output Enable Input. This signal must be asserted LOW to enable the I/O data pins during read  
operations.  
R/WL  
R/WR  
Read/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.  
For read operations, assert this pin HIGH.  
FT/PIPEL  
FT/PIPER  
Flow-Through/Pipelined Select Input. For flow-through mode operation, assert this pin LOW.  
For pipelined mode operation, assert this pin HIGH.  
GND  
NC  
Ground Input.  
No Connect.  
Power Input.  
VCC  
Maximum Ratings[6]  
DC Input Voltage ............................................–0.5V to +7.0V  
Output Current into Outputs (LOW)............................. 20 mA  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Static Discharge Voltage............................................ >1100V  
Latch-Up Current..................................................... >200 mA  
Storage Temperature ................................. –65°C to +150°C  
Ambient Temperature with Power Applied..–55°C to +125°C  
Supply Voltage to Ground Potential............... –0.3V to +7.0V  
Operating Range  
Ambient  
Temperature  
DC Voltage Applied to  
Outputs in High Z State.................................. –0.5V to +7.0V  
Range  
VCC  
Commercial  
0°C to +70°C  
5V ± 10%  
Note:  
6. The Voltage on any input or I/O pin cannot exceed the power pin during power-up.  
Document #: 38-06050 Rev. *A  
Page 4 of 17  
1234567...18

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