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CY7C09179V-7AC PDF预览

CY7C09179V-7AC

更新时间: 2024-02-03 20:46:03
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
18页 335K
描述
3.3V 32K/64K/128K x 8/9 Synchronous Dual-Port Static RAM

CY7C09179V-7AC 技术参数

生命周期:Obsolete零件包装代码:QFP
包装说明:LFQFP,针数:100
Reach Compliance Code:unknownECCN代码:3A991.B.2.B
HTS代码:8542.32.00.41风险等级:5.79
最长访问时间:18 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码:S-PQFP-G100长度:14 mm
内存密度:294912 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:9功能数量:1
端子数量:100字数:32768 words
字数代码:32000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32KX9封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
认证状态:Not Qualified座面最大高度:1.6 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD宽度:14 mm
Base Number Matches:1

CY7C09179V-7AC 数据手册

 浏览型号CY7C09179V-7AC的Datasheet PDF文件第5页浏览型号CY7C09179V-7AC的Datasheet PDF文件第6页浏览型号CY7C09179V-7AC的Datasheet PDF文件第7页浏览型号CY7C09179V-7AC的Datasheet PDF文件第9页浏览型号CY7C09179V-7AC的Datasheet PDF文件第10页浏览型号CY7C09179V-7AC的Datasheet PDF文件第11页 
CY7C09079V/89V/99V  
CY7C09179V/89V/99V  
Switching Waveforms (continued)  
Read Cycle for Flow-Through Output (FT/PIPE = VIL)[16, 17, 18, 19]  
t
CYC1  
t
t
CL1  
CH1  
CLK  
CE  
CE  
0
1
t
t
t
t
HC  
SC  
HC  
SC  
R/W  
t
t
t
t
SW  
SA  
HW  
HA  
A
A
A
A
n+3  
n
n+1  
n+2  
ADDRESS  
t
CKHZ  
t
t
DC  
CD1  
DATA  
OUT  
Q
Q
t
Q
n
n+1  
n+2  
DC  
t
t
CKLZ  
t
OHZ  
OLZ  
OE  
t
OE  
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[16, 17, 18, 19]  
t
CYC2  
t
t
CL2  
CH2  
CLK  
CE  
CE  
0
1
t
t
t
t
HC  
SC  
HC  
SC  
R/W  
t
t
t
t
SW  
SA  
HW  
HA  
ADDRESS  
A
A
A
A
n+3  
n
n+1  
n+2  
t
1 Latency  
t
DC  
CD2  
DATA  
OUT  
Q
Q
Q
n+2  
n
n+1  
t
OHZ  
t
t
CKLZ  
OLZ  
OE  
tOE  
Notes:  
16. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.  
17. ADS = VIL, CNTEN and CNTRST = VIH  
18. The output is disabled (high-impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock.  
19. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only.  
.
Document #: 38-06043 Rev. *A  
Page 8 of 18  

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