Datasheet > CY7C0831AV_12

CY7C0831AV_12

更新时间： 2024-11-07 12:21:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
31页	526K
描述
FLEx18â¢ 3.3 V 128 K / 256 K / 512 K Ã 18 Synchronous Dual-Port RAM

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CY7C0831AV_12 数据手册

CY7C0831AV, CY7C0832AV

CY7C0832BV, CY7C0833V

FLEx18™ 3.3 V 128 K / 256 K / 512 K × 18

Synchronous Dual-Port RAM

FLEx18™ 3.3

V 128 K / 256 K / 512 K × 18 Synchronous Dual-Port RAM

Features

Functional Description

■ True dual-ported memory cells that allow simultaneous access

of the same memory location

The FLEx18™ family includes 2-Mbit, 4-Mbit, and 9-Mbit

pipelined, synchronous, true dual port static RAMs that are high

speed, low power 3.3 V CMOS. Two ports are provided,

permitting independent, simultaneous access to any location in

memory. The result of writing to the same location by more than

one port at the same time is undefined. Registers on control,

address, and data lines allow for minimal setup and hold time.

■ Synchronous pipelined operation

■ Family of 2-Mbit, 4-Mbit, and 9-Mbit devices

■ Pipelined output mode allows fast operation

■ 0.18 micron CMOS for optimum speed and power

■ High speed clock to data access

During a Read operation, data is registered for decreased cycle

time. Each port contains a burst counter on the input address

address, the counter increments the address internally (more

details to follow). The internal Write pulse width is independent

of the duration of the R/W input signal. The internal Write pulse

is self-timed to allow the shortest possible cycle times.

■ 3.3 V low power

❐ Active as low as 225 mA (typ)

❐ Standby as low as 55 mA (typ)

■ Mailbox function for message passing

■ Global master reset

A HIGH on CE₀or LOW on CE₁for one clock cycle powers down

the internal circuitry to reduce the static power consumption. One

cycle with chip enables asserted is required to reactivate the

outputs.

■ Separate byte enables on both ports

■ Commercial and Industrial temperature ranges

■ IEEE 1149.1 compatible JTAG boundary scan

■ 144-ball FBGA (13 mm × 13 mm) (1.0 mm pitch)

■ 120-pin TQFP (14 mm × 14 mm × 1.4 mm)

■ Pb-free packages available

Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap around, counter interrupt (CNTINT)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST).

The CY7C0833V device in this family has limited features. See

Address Counter and Mask Register Operations on page 7 for

details.

■ Counter wrap around control

❐ Internal mask register controls counter wrap around

❐ Counter-interrupt flags to indicate wrap around

❐ Memory block retransmit operation

■ Counter readback on address lines

■ Mask register readback on address lines

■ Dual chip enables on both ports for easy depth expansion

Product Selection Guide

2 Mbit

(128 K × 18)

4 Mbit

(256 K × 18)

9 Mbit

(512 K × 18)

Density

Part Number

CY7C0831AV

CY7C0832AV

CY7C0832BV ^[1]

CY7C0833V

Maximum Speed (MHz)

Maximum Access Time - Clock to Data (ns)

Typical Operating Current (mA)

Package

133

4.0

167

4.0

133

4.4

100

4.7

225

270

120-pin TQFP

144-ball FBGA

Note

1. CY7C0832AV and CY7C0832BV are functionally identical.

Cypress Semiconductor Corporation

Document #: 38-06059 Rev. *W

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised October 13, 2011

12 3 4 5 6 7...31

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与CY7C0831AV_12相关器件

型号	品牌	获取价格	描述	数据表
CY7C0831AV-133AC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0831AV-133AI	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0831AV-133AXC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0831AV-133AXI	CYPRESS	获取价格	FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
CY7C0831AV-133BBC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0831AV-133BBI	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0831AV-133BBI	ROCHESTER	获取价格	128KX18 DUAL-PORT SRAM, 4ns, PBGA144, 13 X 13 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-144
CY7C0831AV-133BBXC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0831AV-133BBXI	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0831AV-167AC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18

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