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CY7C0831AV-133AXI PDF预览

CY7C0831AV-133AXI

更新时间: 2024-11-07 11:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
28页 673K
描述
FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM

CY7C0831AV-133AXI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFP包装说明:LFQFP, QFP120,.63SQ,16
针数:120Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.73最长访问时间:4 ns
其他特性:PIPELINED ARCHITECTURE最大时钟频率 (fCLK):133 MHz
I/O 类型:COMMONJESD-30 代码:S-PQFP-G120
JESD-609代码:e3长度:14 mm
内存密度:2359296 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:18湿度敏感等级:3
功能数量:1端口数量:2
端子数量:120字数:131072 words
字数代码:128000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:128KX18输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:LFQFP
封装等效代码:QFP120,.63SQ,16封装形状:SQUARE
封装形式:FLATPACK, LOW PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3.3 V
认证状态:Not Qualified座面最大高度:1.6 mm
最大待机电流:0.075 A最小待机电流:3.14 V
子类别:SRAMs最大压摆率:0.3 mA
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.4 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:14 mm
Base Number Matches:1

CY7C0831AV-133AXI 数据手册

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CY7C0837AV, CY7C0830AV  
CY7C0831AV, CY7C0832AV  
CY7C0832BV, CY7C0833AV  
FLEx18™ 3.3V 64K/128K x 36 and  
128K/256K x 18 Synchronous Dual-Port RAM  
Features  
Functional Description  
True Dual-Ported Memory Cells that Allow Simultaneous  
Access of the Same Memory Location  
The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit,  
and 9 Mbit pipelined, synchronous, true dual port static RAMs  
that are high speed, low power 3.3V CMOS. Two ports are  
provided, permitting independent, simultaneous access to any  
location in memory. The result of writing to the same location by  
more than one port at the same time is undefined. Registers on  
control, address, and data lines allow for minimal setup and hold  
time.  
Synchronous Pipelined Operation  
Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices  
Pipelined Output Mode Allows Fast Operation  
0.18 micron CMOS for Optimum Speed and Power  
High Speed Clock to Data Access  
During a Read operation, data is registered for decreased cycle  
time. Each port contains a burst counter on the input address  
register. After externally loading the counter with the initial  
address, the counter increments the address internally (more  
details to follow). The internal Write pulse width is independent  
of the duration of the R/W input signal. The internal Write pulse  
is self-timed to allow the shortest possible cycle times.  
3.3V Low Power  
Active as Low as 225 mA (typ)  
Standby as Low as 55 mA (typ)  
Mailbox Function for Message Passing  
Global Master Reset  
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down  
the internal circuitry to reduce the static power consumption. One  
cycle with chip enables asserted is required to reactivate the  
outputs.  
Separate Byte Enables on Both Ports  
Commercial and Industrial Temperature Ranges  
IEEE 1149.1 Compatible JTAG Boundary Scan  
144-Ball FBGA (13 mm × 13 mm) (1.0 mm pitch)  
120 TQFP (14 mm x 14 mm x 1.4 mm)  
Pb-Free Packages Available  
Additional features include: readback of burst-counter internal  
address value on address lines, counter-mask registers to  
control the counter wrap around, counter interrupt (CNTINT)  
flags, readback of mask register value on address lines,  
retransmit functionality, interrupt flags for message passing,  
JTAG for boundary scan, and asynchronous Master Reset  
(MRST).  
Counter Wrap Around Control  
The CY7C0833AV device in this family has limited features. See  
Address Counter and Mask Register Operations [16] on page 6  
for details.  
Internal Mask Register Controls Counter Wrap Around  
Counter-Interrupt Flags to Indicate Wrap Around  
Memory Block Retransmit Operation  
Counter Readback on Address Lines  
Mask Register Readback on Address Lines  
Dual Chip Enables on Both Ports for Easy Depth Expansion  
Table 1. Product Selection Guide  
512 Kbit  
1 Mbit  
2 Mbit  
4 Mbit  
9 Mbit  
Density  
(32K x 18)  
CY7C0837AV  
167  
(64K x 18)  
(128K x 18)  
(256K x 18)  
(512K x 18)  
Part Number  
CY7C0830AV  
CY7C0831AV  
CY7C0832AV CY7C0832BV [1] CY7C0833AV  
Maximum Speed (MHz)  
167  
4.0  
167  
4.0  
167  
4.0  
133  
4.4  
133  
4.7  
Maximum Access Time -  
Clock to Data (ns)  
4.0  
Typical Operating  
Current (mA)  
225  
225  
225  
225  
225  
270  
Package  
144 FBGA  
120 TQFP  
144 FBGA  
120 TQFP  
144 FBGA  
120 TQFP  
144 FBGA  
120 TQFP  
144 FBGA  
Note  
1. CY7C0832AV and CY7C0832BV are functionally identical.  
Cypress Semiconductor Corporation  
Document #: 38-06059 Rev. *S  
198 Champion Court  
San Jose  
,
CA 95134-1709  
408-943-2600  
Revised March 03, 2009  
[+] Feedback  

CY7C0831AV-133AXI 替代型号

型号 品牌 替代类型 描述 数据表
CY7C0831AV-167AXC CYPRESS

类似代替

FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
CY7C0831V-167AXC CYPRESS

功能相似

Dual-Port SRAM, 128KX18, 4ns, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-1

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