Datasheet > CY7C0831V-167AXC

CY7C0831V-167AXC

更新时间： 2024-09-19 07:52:43

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器内存集成电路
页数	文件大小	规格书
32页	895K
描述
Dual-Port SRAM, 128KX18, 4ns, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120

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CY7C0831V-167AXC 技术参数

是否Rohs认证：	符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP-120
针数：	120	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	5.64	最长访问时间：	4 ns
其他特性：	PIPELINED ARCHITECTURE	JESD-30 代码：	S-PQFP-G120
长度：	14 mm	内存密度：	2359296 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	18
功能数量：	1	端子数量：	120
字数：	131072 words	字数代码：	128000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	128KX18
封装主体材料：	PLASTIC/EPOXY	封装代码：	LFQFP
封装形状：	SQUARE	封装形式：	FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：	PARALLEL	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子形式：	GULL WING
端子节距：	0.4 mm	端子位置：	QUAD
宽度：	14 mm	Base Number Matches：	1

CY7C0831V-167AXC 数据手册

CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K

Synchronous Dual-Port RAM

x 36 and 128K/256K x 18

CY7C0851V/CY7C0852V

CY7C0831V/CY7C0832V

3.3V 64K/128K x 36 and 128K/256K x 18

Synchronous Dual-Port RAM

Functional Description

Features

• True dual-ported memory cells that allow simultaneous

access of the same memory location

• Synchronous pipelined operation

• Organization of 2M and 4.5M devices

— 128K × 36 (CY7C0852V)

The CY7C0851V/CY7C0852V/CY7C0831VCY7C0832V are

2M and 4.5M pipelined, synchronous, true dual-port static

RAMs that are high-speed, low-power 3.3V CMOS. Two ports

are provided, permitting independent, simultaneous access for

Reads from any location in memory. The result of writing to the

same location by more than one port at the same time is

undefined. Registers on control, address, and data lines allow

for minimal set-up and hold time.

— 64K × 36 (CY7C0851V)

— 256K × 18 (CY7C0832V)

During a Read operation, data is registered for decreased

cycle time. Clock to data valid t_CD2= 4.0 ns at 167 MHz. Each

port contains a burst counter on the input address register.

After externally loading the counter with the initial address, the

counter will increment the address internally (more details to

follow). The internal Write pulse width is independent of the

duration of the R/W input signal. The internal Write pulse is

self-timed to allow the shortest possible cycle times.

— 128K × 18 (CY7C0831V)

• Pipelined output mode allows fast 167-MHz operation

• 0.18-micron CMOS for optimum speed and power

• High-speed clock to data access: 4.0 ns (max.)

• 3.3V low operating power

—Active = 225 mA (typical)

— Standby = 55 mA (typical)

A HIGH on CE0 or LOW on CE1 for one clock cycle will power

down the internal circuitry to reduce the static power

consumption. One cycle with chip enables asserted is required

to reactivate the outputs.

• Interrupt flags for message passing

• Global master reset

• Separate byte enables on both ports

• Commercial and industrial temperature ranges

• IEEE 1149.1-compatible JTAG boundary scan

• 172-ball BGA (1 mm pitch) (15 mm × 15 mm)

• 120-pin TQFP (14 mm × 14 mm × 1.4 mm)

• 176-pin TQFP (24 mm × 24 mm × 1.4 mm)

• FLEx36™ devices are footprint upgradeable from 2M to

4M to 9M

• Counter wrap around control

Counter enable (CNTEN) inputs are provided to stall the

operation of the address input and utilize the internal address

generated by the internal counter for fast, interleaved memory

applications. A port’s burst counter is loaded when the port’s

address strobe (ADS) and CNTEN signals are LOW. When the

port’s CNTEN is asserted and the ADS is deasserted, the

address counter will increment on each LOW to HIGH

transition of that port’s clock signal. This will Read/Write one

word from/into each successive address location until CNTEN

is deasserted. The counter can address the entire memory

array, and will loop back to the start. Counter reset (CNTRST)

is used to reset the unmasked portion of the burst counter to

0s. A counter-mask register is used to control the counter

wrap. The counter and mask register operations are described

in more detail in the following sections.

— Internal mask register controls counter wrap-around

— Counter-interrupt flags to indicate wrap-around

— Memory block retransmit operation

• Counter readback on address lines

• Mask register readback on address lines

• Dual Chip Enables on both ports for easy depth

expansion

New features added to the CY7C0851V/CY7C0852V/

CY7C0831V/CY7C0832V devices include: readback of

burst-counter internal address value on address lines,

counter-mask registers to control the counter wrap-around,

counter interrupt (CNTINT) flags, readback of mask register

value on address lines, retransmit functionality, interrupt flags

for message passing, JTAG for boundary scan, and

asynchronous Master Reset (MRST).

Cypress offers an upgrade to a 9M synchronous Dual Port with

a compatible footprint. Please see the application note

Upgrading the 4-Meg (CY7C0852) Dual-Port to a 9-Meg

(CY7C0853) Dual-Port for more details.

Cypress Semiconductor Corporation

Document #: 38-06059 Rev. *I

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised June 03, 2004

12 3 4 5 6 7...32

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CY7C0831V-167AXC 替代型号

型号	品牌	替代类型	描述	数据表
CY7C0831AV-133AXI	CYPRESS	功能相似	FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
CY7C0831AV-167AC	CYPRESS	功能相似	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18

与CY7C0831V-167AXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C0831V-167BBC	CYPRESS	获取价格	FLEx18-TM 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM
CY7C0831V-167BBI	CYPRESS	获取价格	FLEx18-TM 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM
CY7C0832AV	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-133AC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-133AI	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-133AXC	CYPRESS	获取价格	FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
CY7C0832AV-133AXI	CYPRESS	获取价格	FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
CY7C0832AV-133BBC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-133BBC	ROCHESTER	获取价格	256KX18 DUAL-PORT SRAM, 4ns, PBGA144, 13 X 13 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-144
CY7C0832AV-133BBI	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18

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