CY7C0831V-167BBC

更新时间： 2024-11-07 09:43:15

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
28页	446K
描述
FLEx18-TM 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM

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CY7C0831V-167BBC 数据手册

CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389V3.3V 64K/128K

Synchronous Dual-Port RAM

x 36 and 128K/256K x 18

CY7C0837V

CY7C0830V/CY7C0831V

CY7C0832V/CY7C0833V

PRELIMINARY

FLEx18 3.3V 32K/64K/128K/256K/512K x 18

Synchronous Dual-Port RAM

Functional Description

Features

• True dual-ported memory cells that allow simultaneous

access of the same memory location

• Synchronous pipelined operation

• Family of 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit

devices

• Pipelined output mode allows fast operation

• 0.18-micron CMOS for optimum speed and power

• High-speed clock to data access

• 3.3V low power

The FLEx18 family includes 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit

and 9-Mbit pipelined, synchronous, true dual-port static RAMs

that are high-speed, low-power 3.3V CMOS. Two ports are

provided, permitting independent, simultaneous access to any

location in memory. The result of writing to the same location

by more than one port at the same time is undefined. Registers

on control, address, and data lines allow for minimal set-up

and hold time.

During a Read operation, data is registered for decreased

cycle time. Each port contains a burst counter on the input

address register. After externally loading the counter with the

initial address, the counter will increment the address inter-

nally (more details to follow). The internal Write pulse width is

independent of the duration of the R/W input signal. The

internal Write pulse is self-timed to allow the shortest possible

cycle times.

—Active as low as 225 mA (typ)

— Standby as low as 55 mA (typ)

• Mailbox function for message passing

• Global master reset

• Separate byte enables on both ports

• Commercial and industrial temperature ranges

• IEEE 1149.1-compatible JTAG boundary scan

• 144-ball FBGA (13 mm × 13 mm) (1.0 mm pitch)

• 120TQFP (14 mm x 14 mm x 1.4 mm)

• Counter wrap around control

A HIGH on CE0 or LOW on CE1 for one clock cycle will power

down the internal circuitry to reduce the static power

consumption. One cycle with chip enables asserted is required

to reactivate the outputs.

Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap-around, counter interrupt (CNTINT)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST).

— Internal mask register controls counter wrap-around

— Counter-interrupt flags to indicate wrap-around

— Memory block retransmit operation

• Counter readback on address lines

• Mask register readback on address lines

• Dual Chip Enables on both ports for easy depth

expansion

The CY7C0833V device in this family has limited features.

Please see Address Counter and Mask Register

Operations^[15]on page 6 for details.

Table 1. Product Selection Guide

Density

512-Kbit

(32K x 18)

1-Mbit

(64K x 18)

2-Mbit

(128K x 18)

4-Mbit

(256K x 18)

9-Mbit

(512K x 18)

Part Number

CY7C0837V

167

CY7C0830V

CY7C0831V

CY7C0832V

CY7C0833V

133

Max. Speed (MHz)

167

4.0

167

4.0

167

4.0

Max. Access Time - clock to Data (ns)

Typical operating current (mA)

Package

4.0

4.7

225

270

144 FBGA

120 TQFP

144 FBGA

120 TQFP

144 FBGA

120 TQFP

144 FBGA

Cypress Semiconductor Corporation

Document #: 38-06059 Rev. *K

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

July 06, 2004

12 3 4 5 6 7...28

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与CY7C0831V-167BBC相关器件

型号	品牌	获取价格	描述	数据表
CY7C0831V-167BBI	CYPRESS	获取价格	FLEx18-TM 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM
CY7C0832AV	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-133AC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-133AI	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-133AXC	CYPRESS	获取价格	FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
CY7C0832AV-133AXI	CYPRESS	获取价格	FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
CY7C0832AV-133BBC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-133BBC	ROCHESTER	获取价格	256KX18 DUAL-PORT SRAM, 4ns, PBGA144, 13 X 13 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-144
CY7C0832AV-133BBI	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-167AC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18

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