Datasheet > 存储 > SRAM> CY7C0832AV-133AXI

CY7C0832AV-133AXI

更新时间： 2024-09-18 06:51:39

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
28页	673K
描述
FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM

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CY7C0837AV, CY7C0830AV

CY7C0831AV, CY7C0832AV

CY7C0832BV, CY7C0833AV

FLEx18™ 3.3V 64K/128K x 36 and

128K/256K x 18 Synchronous Dual-Port RAM

Features

Functional Description

■

True Dual-Ported Memory Cells that Allow Simultaneous

Access of the Same Memory Location

The FLEx18™ family includes 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit,

and 9 Mbit pipelined, synchronous, true dual port static RAMs

that are high speed, low power 3.3V CMOS. Two ports are

provided, permitting independent, simultaneous access to any

location in memory. The result of writing to the same location by

more than one port at the same time is undefined. Registers on

control, address, and data lines allow for minimal setup and hold

time.

■

Synchronous Pipelined Operation

Family of 512 Kbit, 1 Mbit, 2 Mbit, 4 Mbit, and 9 Mbit Devices

Pipelined Output Mode Allows Fast Operation

0.18 micron CMOS for Optimum Speed and Power

High Speed Clock to Data Access

During a Read operation, data is registered for decreased cycle

time. Each port contains a burst counter on the input address

address, the counter increments the address internally (more

details to follow). The internal Write pulse width is independent

of the duration of the R/W input signal. The internal Write pulse

is self-timed to allow the shortest possible cycle times.

3.3V Low Power

❐

Active as Low as 225 mA (typ)

Standby as Low as 55 mA (typ)

❐

■

Mailbox Function for Message Passing

Global Master Reset

A HIGH on CE0 or LOW on CE1 for one clock cycle powers down

the internal circuitry to reduce the static power consumption. One

cycle with chip enables asserted is required to reactivate the

outputs.

Separate Byte Enables on Both Ports

Commercial and Industrial Temperature Ranges

IEEE 1149.1 Compatible JTAG Boundary Scan

144-Ball FBGA (13 mm × 13 mm) (1.0 mm pitch)

120 TQFP (14 mm x 14 mm x 1.4 mm)

Pb-Free Packages Available

Additional features include: readback of burst-counter internal

address value on address lines, counter-mask registers to

control the counter wrap around, counter interrupt (CNTINT)

flags, readback of mask register value on address lines,

retransmit functionality, interrupt flags for message passing,

JTAG for boundary scan, and asynchronous Master Reset

(MRST).

Counter Wrap Around Control

The CY7C0833AV device in this family has limited features. See

Address Counter and Mask Register Operations ^[16]on page 6

for details.

❐

Internal Mask Register Controls Counter Wrap Around

Counter-Interrupt Flags to Indicate Wrap Around

Memory Block Retransmit Operation

■

Counter Readback on Address Lines

Mask Register Readback on Address Lines

Dual Chip Enables on Both Ports for Easy Depth Expansion

Table 1. Product Selection Guide

512 Kbit

1 Mbit

2 Mbit

4 Mbit

9 Mbit

Density

(32K x 18)

CY7C0837AV

167

(64K x 18)

(128K x 18)

(256K x 18)

(512K x 18)

Part Number

CY7C0830AV

CY7C0831AV

CY7C0832AV CY7C0832BV ^[1]CY7C0833AV

Maximum Speed (MHz)

167

4.0

167

4.0

167

4.0

133

4.4

133

4.7

Maximum Access Time -

Clock to Data (ns)

4.0

Typical Operating

Current (mA)

225

270

Package

144 FBGA

120 TQFP

144 FBGA

120 TQFP

144 FBGA

120 TQFP

144 FBGA

120 TQFP

144 FBGA

Note

1. CY7C0832AV and CY7C0832BV are functionally identical.

Cypress Semiconductor Corporation

Document #: 38-06059 Rev. *S

•

198 Champion Court

•

San Jose

CA 95134-1709

•

408-943-2600

Revised March 03, 2009

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CY7C0832AV-133AXI 替代型号

型号	品牌	替代类型	描述	数据表
CY7C0832V-133AXI	CYPRESS	完全替代	暂无描述
CY7C0832V-133AXC	CYPRESS	完全替代	Dual-Port SRAM, 256KX18, 4.4ns, CMOS, PQFP120, 14 X 14 MM, 1.40 MM HEIGHT, LEAD FREE, TQFP
CY7C0832BV-133AI	CYPRESS	完全替代	FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM

与CY7C0832AV-133AXI相关器件

型号	品牌	获取价格	描述	数据表
CY7C0832AV-133BBC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-133BBC	ROCHESTER	获取价格	256KX18 DUAL-PORT SRAM, 4ns, PBGA144, 13 X 13 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-144
CY7C0832AV-133BBI	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-167AC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-167AXC	CYPRESS	获取价格	FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
CY7C0832AV-167BBC	CYPRESS	获取价格	FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0832AV-167BBC	ROCHESTER	获取价格	256KX18 DUAL-PORT SRAM, 4ns, PBGA144, 13 X 13 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-144
CY7C0832BV	CYPRESS	获取价格	FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
CY7C0832BV-133AI	CYPRESS	获取价格	FLEx18 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM
CY7C0832V	CYPRESS	获取价格	FLEx18-TM 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM

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