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CY7C016-25AC PDF预览

CY7C016-25AC

更新时间: 2024-09-17 04:53:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
16页 322K
描述
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy

CY7C016-25AC 数据手册

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with Sem, In t, Busy  
CY7C006  
CY7C016  
16K x 8/9 Dual-Port Static RAM  
with Sem, Int, Busy  
schemes are included on the CY7C006/016 to handle situa-  
tions when multiple processors access the same piece of data.  
Two ports are provided, permitting independent, asynchro-  
nous access for reads and writes to any location in memory.  
Features  
• True dual-ported memory cells which allow  
simultaneous reads of the same memory location  
The CY7C006/016 can be utilized as  
a standalone  
• 16K x 8 organization (CY7C006)  
• 16K x 9 organization (CY7C016)  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15 ns  
128-/144-Kbit dual-port static RAM or multiple devices can be  
combined in order to function as a 16-/18-bit or wider mas-  
ter/slave dual-port static RAM. An M/S pin is provided for im-  
plementing 16-/18-bit or wider memory applications without  
the need for separate master and slave devices or additional  
discrete logic. Application areas include interprocessor/multi-  
processor designs, communications status buffering, and du-  
al-port video/graphics memory.  
• Low operating power: I = 140 mA (typ.)  
CC  
• Fully asynchronous operation  
• Automatic power-down  
• TTL compatible  
Each port has independent control pins: Chip Enable (CE),  
Read or Write Enable (R/W), and Output Enable (OE). Two  
flags, BUSY and INT, are provided on each port. BUSY signals  
that the port is trying to access the same location currently  
being accessed by the other port. The Interrupt flag (INT) per-  
mits communication between ports or systems by means of a  
mail box. The semaphores are used to pass a flag, or token,  
from one port to the other to indicate that a shared resource is  
in use. The semaphore logic is comprised of eight shared  
latches. Only one side can control the latch (semaphore) at  
any time. Control of a semaphore indicates that a shared re-  
source is in use. An automatic power-down feature is con-  
trolled independently on each port by a Chip Enable (CE) pin  
or SEM pin.  
• Expandable data bus to 16/18 bits or more using  
Master/Slave chip select when using more than one  
device  
• Busy arbitration scheme provided  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Available in 68-pin PLCC (7C006), 64-pin (7C006) and  
80-pin (7C016) TQFP  
• Pin compatible and functional equivalent to  
IDT7006/IDT7016  
Functional Description  
The CY7C006 and CY7C016 are available in 68-pin PLCC  
(CY7C006), 64-pin (CY7C006) TQFP, and 80-pin (CY7C016) TQFP.  
The CY7C006 and CY7C016 are high-speed CMOS 16K x 8  
and 16K x 9 dual-port static RAMs. Various arbitration  
R/W  
L
R/W  
R
Logic Block Diagram  
CE  
OE  
CE  
OE  
L
R
R
L
(7C016)I/O  
I/O  
I/O (7C016)  
8R  
8L  
7L  
I/O  
7R  
I/O  
CONTROL  
I/O  
CONTROL  
I/O  
0L  
I/O  
0R  
[1,2]  
BUSY  
R
[1,2]  
L
BUSY  
A
13L  
A
A
13R  
0R  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
MEMORY  
ARRAY  
A
0L  
INTERRUPT  
SEMAPHORE  
ARBITRATION  
CE  
OE  
L
L
L
CE  
R
OE  
R
R/W  
R/W  
R
SEM  
SEM  
R
L
[2]  
C006-1  
[2]  
INT  
R
INT  
L
M/S  
Notes:  
1. BUSY is an output in master mode and an input in slave mode.  
2. Interrupt: push-pull output and requires no pull-up resistor.  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
December 22, 1999  

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