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CY7C016AV-25JC PDF预览

CY7C016AV-25JC

更新时间: 2024-11-06 22:20:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
20页 303K
描述
3.3V 4K/8K/16K/32K x 8/9 Dual-Port Static RAM

CY7C016AV-25JC 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LCC包装说明:PLASTIC, LCC-68
针数:68Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.84最长访问时间:25 ns
I/O 类型:COMMONJESD-30 代码:S-PQCC-J68
JESD-609代码:e0长度:24.2316 mm
内存密度:147456 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:9功能数量:1
端口数量:2端子数量:68
字数:16384 words字数代码:16000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:16KX9
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:QCCJ封装等效代码:LDCC68,1.0SQ
封装形状:SQUARE封装形式:CHIP CARRIER
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:3.3 V认证状态:Not Qualified
座面最大高度:5.08 mm最大待机电流:0.00005 A
最小待机电流:2 V子类别:SRAMs
最大压摆率:0.165 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:J BEND端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:24.2316 mmBase Number Matches:1

CY7C016AV-25JC 数据手册

 浏览型号CY7C016AV-25JC的Datasheet PDF文件第2页浏览型号CY7C016AV-25JC的Datasheet PDF文件第3页浏览型号CY7C016AV-25JC的Datasheet PDF文件第4页浏览型号CY7C016AV-25JC的Datasheet PDF文件第5页浏览型号CY7C016AV-25JC的Datasheet PDF文件第6页浏览型号CY7C016AV-25JC的Datasheet PDF文件第7页 
25/0251  
CY7C138AV/144AV/006AV  
CY7C139AV/145AV/016AV  
CY7C007AV/017AV  
3.3V 4K/8K/16K/32K x 8/9  
Dual-Port Static RAM  
• Fully asynchronous operation  
• Automatic power-down  
Features  
• True Dual-Ported memory cells which allow simulta-  
neous access of the same memory location  
• 4K/8K/16K/32K x 8 organizations  
(CY7C0138AV/144AV/006AV/007AV)  
• 4K/8K/16K/32K x 9 organizations  
(CY7C0139AV/145AV/016AV/017AV)  
• 0.35-micron CMOS for optimum speed/power  
• High-speed access: 20/25 ns  
• Low operating power  
• Expandabledatabusto16/18bitsormoreusingMaster/  
Slave chip select when using more than one device  
• On-chip arbitration logic  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Pin select for Master or Slave  
• Commercial and Industrial Temperature Ranges  
• Available in 68-pin PLCC (all) and 64-pin TQFP  
(7C006AV & 7C144AV)  
— Active: ICC = 115 mA (typical)  
— Standby: ISB3 = 10 µA (typical)  
• Pin-compatible and functionally equivalent to  
IDT70V05, 70V06, and 70V07.  
Logic Block Diagram  
R/WL  
CEL  
R/WR  
CER  
OEL  
OER  
[1]  
[1]  
8/9  
8/9  
I/O0LI/O7/8L  
I/O0RI/O7/8R  
I/O  
Control  
I/O  
Control  
[2]  
1215  
1215  
[2]  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
A0LA1114L  
A0RA1114R  
RAM Array  
1215  
1215  
[2]  
[2]  
A0LA1114L  
A0RA1114R  
CEL  
CER  
OER  
Interrupt  
Semaphore  
Arbitration  
OEL  
R/WL  
SEML  
R/WR  
SEMR  
[3]  
BUSYL  
INTL  
[3] BUSYR  
INTR  
M/S  
Notes:  
1. I/O0I/O7 for x8 devices; I/O0I/O8 for x9 devices.  
2. A0A11 for 4K devices; A0A12 for 8K devices; A0A13 for 16K devices; A0A14 for 32K devices;  
3. BUSY is an output in master mode and an input in slave mode.  
For the most recent information, visit the Cypress web site at www.cypress.com  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
Document #: 38-06051 Rev. *A  
Revised December 27, 2002  

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