Datasheet > 存储 > SRAM> CY7C016-35JCR

CY7C016-35JCR

更新时间： 2024-11-07 13:07:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
16页	322K
描述
Multi-Port SRAM, 16KX9, 35ns, CMOS, PQCC68, PLASTIC, LCC-68

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技术参数
数据手册

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CY7C016-35JCR 技术参数

生命周期：	Obsolete	零件包装代码：	LCC
包装说明：	QCCJ,	针数：	68
Reach Compliance Code：	unknown	ECCN代码：	EAR99
HTS代码：	8542.32.00.41	风险等级：	5.78
Is Samacsys：	N	最长访问时间：	35 ns
其他特性：	INTERRUPT FLAG	JESD-30 代码：	S-PQCC-J68
长度：	24.2316 mm	内存密度：	147456 bit
内存集成电路类型：	MULTI-PORT SRAM	内存宽度：	9
功能数量：	1	端口数量：	2
端子数量：	68	字数：	16384 words
字数代码：	16000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	16KX9	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装形状：	SQUARE
封装形式：	CHIP CARRIER	并行/串行：	PARALLEL
认证状态：	Not Qualified	座面最大高度：	5.08 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	4.5 V
标称供电电压 (Vsup)：	5 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	QUAD	宽度：	24.2316 mm
Base Number Matches：	1

CY7C016-35JCR 数据手册

with Sem, In t, Busy

CY7C006

CY7C016

16K x 8/9 Dual-Port Static RAM

with Sem, Int, Busy

schemes are included on the CY7C006/016 to handle situa-

tions when multiple processors access the same piece of data.

Two ports are provided, permitting independent, asynchro-

nous access for reads and writes to any location in memory.

Features

• True dual-ported memory cells which allow

simultaneous reads of the same memory location

The CY7C006/016 can be utilized as

a standalone

• 16K x 8 organization (CY7C006)

• 16K x 9 organization (CY7C016)

• 0.65-micron CMOS for optimum speed/power

• High-speed access: 15 ns

128-/144-Kbit dual-port static RAM or multiple devices can be

combined in order to function as a 16-/18-bit or wider mas-

ter/slave dual-port static RAM. An M/S pin is provided for im-

plementing 16-/18-bit or wider memory applications without

the need for separate master and slave devices or additional

discrete logic. Application areas include interprocessor/multi-

processor designs, communications status buffering, and du-

al-port video/graphics memory.

• Low operating power: I = 140 mA (typ.)

• Fully asynchronous operation

• Automatic power-down

• TTL compatible

Each port has independent control pins: Chip Enable (CE),

Read or Write Enable (R/W), and Output Enable (OE). Two

flags, BUSY and INT, are provided on each port. BUSY signals

that the port is trying to access the same location currently

being accessed by the other port. The Interrupt flag (INT) per-

mits communication between ports or systems by means of a

mail box. The semaphores are used to pass a flag, or token,

from one port to the other to indicate that a shared resource is

in use. The semaphore logic is comprised of eight shared

latches. Only one side can control the latch (semaphore) at

any time. Control of a semaphore indicates that a shared re-

source is in use. An automatic power-down feature is con-

trolled independently on each port by a Chip Enable (CE) pin

or SEM pin.

• Expandable data bus to 16/18 bits or more using

Master/Slave chip select when using more than one

device

• Busy arbitration scheme provided

• Semaphores included to permit software handshaking

between ports

• INT flag for port-to-port communication

• Available in 68-pin PLCC (7C006), 64-pin (7C006) and

80-pin (7C016) TQFP

• Pin compatible and functional equivalent to

IDT7006/IDT7016

Functional Description

The CY7C006 and CY7C016 are available in 68-pin PLCC

(CY7C006), 64-pin (CY7C006) TQFP, and 80-pin (CY7C016) TQFP.

The CY7C006 and CY7C016 are high-speed CMOS 16K x 8

and 16K x 9 dual-port static RAMs. Various arbitration

R/W

Logic Block Diagram

(7C016)I/O

I/O

I/O (7C016)

I/O

CONTROL

I/O

CONTROL

I/O

[1,2]

BUSY

[1,2]

BUSY

13L

13R

ADDRESS

DECODER

ADDRESS

DECODER

MEMORY

ARRAY

INTERRUPT

SEMAPHORE

ARBITRATION

R/W

SEM

[2]

C006-1

[2]

INT

M/S

Notes:

1. BUSY is an output in master mode and an input in slave mode.

2. Interrupt: push-pull output and requires no pull-up resistor.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

December 22, 1999

12 3 4 5 6 7...16

中文翻译

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与CY7C016-35JCR相关器件

型号	品牌	获取价格	描述	数据表
CY7C016-55AC	CYPRESS	获取价格	16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C016-55AI	CYPRESS	获取价格	16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
CY7C016-55JC	CYPRESS	获取价格	Dual-Port SRAM, 16KX9, 55ns, CMOS, PQCC68, PLASTIC, LCC-68
CY7C016A	CYPRESS	获取价格	32K/16K x8, 32K/16K x9 Dual-Port Static RAM
CY7C016A-12AC	CYPRESS	获取价格	32K/16K x8, 32K/16K x9 Dual-Port Static RAM
CY7C016A-12AXC	CYPRESS	获取价格	Dual-Port SRAM, 16KX9, 12ns, CMOS, PQFP80, PLASTIC, TQFP-80
CY7C016A-15AC	CYPRESS	获取价格	32K/16K x8, 32K/16K x9 Dual-Port Static RAM
CY7C016A-15AI	CYPRESS	获取价格	Dual-Port SRAM, 16KX9, 15ns, CMOS, PQFP80, PLASTIC, TQFP-80
CY7C016A-15AXC	CYPRESS	获取价格	Dual-Port SRAM, 16KX9, 15ns, CMOS, PQFP80, LEAD FREE, PLASTIC, TQFP-80
CY7C016A-15IC	ETC	获取价格	x9 Dual-Port SRAM

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