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CY62148DV30LL-55SXIT PDF预览

CY62148DV30LL-55SXIT

更新时间: 2024-11-20 19:52:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器光电二极管内存集成电路
页数 文件大小 规格书
15页 374K
描述
Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, PLASTIC, SOIC-32

CY62148DV30LL-55SXIT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete包装说明:0.450 INCH, LEAD FREE, PLASTIC, SOIC-32
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.82
最长访问时间:55 nsI/O 类型:COMMON
JESD-30 代码:R-PDSO-G32JESD-609代码:e4
长度:20.4465 mm内存密度:4194304 bit
内存集成电路类型:STANDARD SRAM内存宽度:8
湿度敏感等级:3功能数量:1
端子数量:32字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP32,.56封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:2.5/3.3 V
认证状态:Not Qualified座面最大高度:2.997 mm
最大待机电流:0.000006 A最小待机电流:1.5 V
子类别:SRAMs最大压摆率:0.01 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.2 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:11.303 mm
Base Number Matches:1

CY62148DV30LL-55SXIT 数据手册

 浏览型号CY62148DV30LL-55SXIT的Datasheet PDF文件第2页浏览型号CY62148DV30LL-55SXIT的Datasheet PDF文件第3页浏览型号CY62148DV30LL-55SXIT的Datasheet PDF文件第4页浏览型号CY62148DV30LL-55SXIT的Datasheet PDF文件第5页浏览型号CY62148DV30LL-55SXIT的Datasheet PDF文件第6页浏览型号CY62148DV30LL-55SXIT的Datasheet PDF文件第7页 
CY62148DV30  
4-Mbit (512 K × 8) MoBL® Static RAM  
4-Mbit (512  
K × 8) MoBL® Static RAM  
Features  
Functional Description  
Temperature Ranges  
Industrial: –40 °C to 85 °C  
The CY62148DV30 [1] is a high-performance CMOS static RAM  
organized as 512K words by 8 bits. This device features  
advanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL) in portable  
applications such as cellular telephones. The device also has an  
automatic power-down feature that significantly reduces power  
consumption. The device can be put into standby mode reducing  
power consumption when deselected (CE HIGH).The eight input  
Very high speed: 55 ns  
Wide voltage range: 2.20 V–3.60 V  
Pin-compatible with CY62148CV25, CY62148CV30 and  
CY62148CV33  
Ultra low active power  
and output pins (I/O0 through I/O7) are placed in  
high-impedance state when:  
a
Typical active current: 1.5 mA at f = 1 MHz  
Typical active current: 8 mA at f = fmax (55-ns speed)  
Ultra low standby power  
Deselected (CE HIGH)  
Easy memory expansion with CE, and OE features  
Automatic power-down when deselected  
Outputs are disabled (OE HIGH)  
When the write operation is active(CE LOW and WE LOW)  
Write to the device by taking Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)  
is then written into the location specified on the address pins (A0  
through A18).  
Complementary metal oxide semiconductor (CMOS) for  
optimum speed/power  
Available in Pb-free 32-pin Small-outline integrated circuit  
(SOIC package)  
Read from the device by taking Chip Enable (CE) and Output  
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under  
these conditions, the contents of the memory location specified  
by the address pins will appear on the I/O pins.  
For a complete list of related documentation, click here.  
Logic Block Diagram  
I/O  
I/O  
0
A0  
Data in Drivers  
A1  
A2  
A3  
A4  
A5  
1
I/O  
2
A6  
I/O  
512K x 8  
ARRAY  
3
A7  
A8  
A9  
I/O  
4
A10  
A11  
A12  
I/O  
5
I/O  
6
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
WE  
OE  
7
Note  
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document Number: 38-05341 Rev. *J  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised November 24, 2017  
 

CY62148DV30LL-55SXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY62148DV30LL-55SXI CYPRESS

完全替代

4-Mb (512K x 8) MoBL Static RAM

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