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CY62148DV30LL-55ZAI PDF预览

CY62148DV30LL-55ZAI

更新时间： 2024-11-20 13:01:39
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 185K
描述
Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP-32

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CY62148DV30LL-55ZAI 技术参数

生命周期：Obsolete零件包装代码：TSOP
包装说明：TSOP1, TSSOP32,.56,20针数：32
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.65
Is Samacsys：N最长访问时间：55 ns
I/O 类型：COMMONJESD-30 代码：R-PDSO-G32
长度：11.8 mm内存密度：4194304 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
功能数量：1端子数量：32
字数：524288 words字数代码：512000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX8
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP1封装等效代码：TSSOP32,.56,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL电源：2.5/3.3 V
认证状态：Not Qualified座面最大高度：1.05 mm
最大待机电流：0.000006 A最小待机电流：1.5 V
子类别：SRAMs最大压摆率：0.01 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL宽度：8 mm
Base Number Matches：1

CY62148DV30LL-55ZAI 数据手册

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CY62148DV30  
4-Mb (512K x 8) MoBLStatic RAM  
Features  
Functional Description[1]  
• Very high speed: 55 ns  
The CY62148DV30 is a high-performance CMOS static RAMs  
organized as 512K words by 8 bits. This device features  
advanced circuit design to provide ultra-low active current.  
— Wide voltage range: 2.20V – 3.60V  
• Pin-compatible with CY62148CV25, CY62148CV30 and  
CY62148CV33  
• Ultra low active power  
This is ideal for providing More Battery Life™ (MoBL) in  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption. The device can be put into  
standby mode reducing power consumption when deselected  
(CE HIGH).  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typical active current: 8 mA @ f = fmax(55-ns speed)  
• Ultra low standby power  
• Easy memory expansion with CE, and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O0 through I/O7) is then written into the location  
specified on the address pins (A0 through A18).  
• Packages offered: 36-ball BGA, 32-pin TSOPII and  
32-pin SOIC  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW and WE LOW).  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
Data in Drivers  
A
0
1
A
A
A
2
3
A
4
5
A
A
A
A
6
512K x 8  
ARRAY  
7
8
A
9
A
10  
A
11  
A12  
6
7
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
WE  
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05341 Rev. *B  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised February 10, 2004  
1234567...11

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