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CY62148E_10 PDF预览

CY62148E_10

更新时间: 2024-11-20 09:42:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
14页 407K
描述
4-Mbit (512 K × 8) Static RAM

CY62148E_10 数据手册

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CY62148E MoBL®  
4-Mbit (512 K × 8) Static RAM  
4-Mbit (512  
K × 8) Static RAM  
Features  
Functional Description  
Very high speed: 45 ns  
The CY62148E is a high performance CMOS static RAM  
organized as 512 K words by 8-bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power-down feature that significantly reduces power  
consumption when addresses are not toggling. Placing the  
device into standby mode reduces power consumption by more  
than 99% when deselected (CE HIGH). The eight input and  
output pins (I/O0 through I/O7) are placed in a high impedance  
state when the device is deselected (CE HIGH), Outputs are  
disabled (OE HIGH), or during an active Write operation (CE  
LOW and WE LOW)  
Voltage range: 4.5 V to 5.5 V  
Pin compatible with CY62148B  
Ultra low standby power  
Typical standby current: 1 µA  
Maximum standby current: 7 µA (Industrial)  
Ultra low active power  
Typical active current: 2.0 mA at f = 1 MHz  
Easy memory expansion with CE, and OE features  
Automatic power-down when deselected  
To write to the device, take Chip Enable (CE) and Write Enable  
(WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7)  
is then written into the location specified on the address pins (A0  
through A18).  
Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
AvailableinPb-free32-pinthinsmalloutlinepackage(TSOP) II  
and 32-pin small-outline integrated circuit (SOIC)[1] packages  
To read from the device, take Chip Enable (CE) and Output  
Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under  
these conditions, the contents of the memory location specified  
by the address pins appear on the I/O pins.  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
A
I/O  
I
0
0
INPUT BUFFER  
A
1
A
2
I/O  
I
1
2
3
4
5
6
7
A
3
A
4
I/O  
I
A
5
A
I/O  
I
6
512K x 8  
A
7
A
I/O  
I
8
ARRAY  
A
9
A
I/O  
I
10  
A
11  
A
I/O  
12  
I
I/O  
CE  
I
POWER  
DOWN  
COLUMN DECODER  
WE  
OE  
Note  
1. SOIC package is available only in 55 ns speed bin.  
Cypress Semiconductor Corporation  
Document #: 38-05442 Rev. *H  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 23, 2010  
[+] Feedback  

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