Datasheet > CY62148E_11

CY62148E_11

更新时间： 2024-11-20 09:42:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
16页	919K
描述
4-Mbit (512 K x 8) Static RAM Automatic power-down when deselected

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CY62148E_11 数据手册

CY62148E MoBL^®

4-Mbit (512 K × 8) Static RAM

4-Mbit (512

K × 8) Static RAM

Features

Functional Description

■ Very high speed: 45 ns

The CY62148E is a high performance CMOS static RAM

organized as 512 K words by 8-bits. This device features

advanced circuit design to provide ultra low active current. This

is ideal for providing More Battery Life™ (MoBL^) in portable

applications such as cellular telephones. The device also has an

automatic power-down feature that significantly reduces power

consumption when addresses are not toggling. Placing the

device into standby mode reduces power consumption by more

than 99% when deselected (CE HIGH). The eight input and

output pins (I/O₀through I/O₇) are placed in a high impedance

state when the device is deselected (CE HIGH), Outputs are

disabled (OE HIGH), or during an active Write operation (CE

LOW and WE LOW)

■ Voltage range: 4.5 V to 5.5 V

■ Pin compatible with CY62148B

■ Ultra low standby power

❐ Typical standby current: 1 µA

❐ Maximum standby current: 7 µA (Industrial)

■ Ultra low active power

❐ Typical active current: 2.0 mA at f = 1 MHz

■ Easy memory expansion with CE, and OE features

■ Automatic power-down when deselected

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. Data on the eight I/O pins (I/O₀through I/O₇)

is then written into the location specified on the address pins (A₀

through A₁₈).

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed and power

■ Available in Pb-free 32-pin thin small outline package (TSOP) II

and 32-pin small-outline integrated circuit (SOIC)^[1]packages

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins appear on the I/O pins.

Logic Block Diagram

I/O

INPUT BUFFER

I/O

512K x 8

I/O

ARRAY

I/O

POWER

DOWN

COLUMN DECODER

Note

1. SOIC package is available only in 55 ns speed bin.

Cypress Semiconductor Corporation

Document #: 38-05442 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 21, 2011

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与CY62148E_11相关器件

型号	品牌	获取价格	描述	数据表
CY62148E_13	CYPRESS	获取价格	4-Mbit (512 K x 8) Static RAM
CY62148ELL	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148ELL-45SXI	CYPRESS	获取价格	Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62148ELL-45ZSXA	CYPRESS	获取价格	4-Mbit (512 K × 8) Static RAM
CY62148ELL-45ZSXA	ROCHESTER	获取价格	512KX8 STANDARD SRAM, 45ns, PDSO32, LEAD FREE, TSOP2-32
CY62148ELL-45ZSXAT	CYPRESS	获取价格	Standard SRAM, 512KX8, 45ns, CMOS, PDSO32
CY62148ELL-45ZSXI	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148ELL-45ZSXI	ROCHESTER	获取价格	Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, LEAD FREE, TSOP2-32
CY62148ELL-45ZSXI	INFINEON	获取价格	Asynchronous SRAM
CY62148ELL-45ZSXIT	CYPRESS	获取价格	Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, 20.95 X 11.76 MM, 1 MM HEIGHT, ROHS COMPLIANT,

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