Datasheet > CY62148E_09

CY62148E_09

更新时间： 2024-11-20 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	934K
描述
4-Mbit (512K x 8) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62148E_09 数据手册

CY62148E MoBL^®

4-Mbit (512K x 8) Static RAM

Features

Functional Description ^[1]

• Very high speed: 45 ns

The CY62148E is a high performance CMOS static RAM

organized as 512K words by 8 bits. This device features

advanced circuit design to provide ultra low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

also has an automatic power down feature that significantly

reduces power consumption when addresses are not toggling.

Placing the device into standby mode reduces power

consumption by more than 99% when deselected (CE HIGH).

The eight input and output pins (IO₀through IO₇) are placed

in a high impedance state when:

• Voltage range: 4.5V–5.5V

• Pin compatible with CY62148B

• Ultra low standby power

— Typical standby current: 1 µA

— Maximum standby current: 7 µA (Industrial)

• Ultra low active power

— Typical active current: 2.0 mA @ f = 1 MHz

• Easy memory expansion with CE, and OE features

• Automatic power down when deselected

• CMOS for optimum speed and power

• Deselected (CE HIGH)

• Outputs are disabled (OE HIGH)

• Write operation is active (CE LOW and WE LOW)

• Available in Pb-free 32-pin TSOP II and 32-pin SOIC ^[2]

packages

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. Data on the eight IO pins (IO₀through IO₇)

is then written into the location specified on the address pins

(A₀through A₁₈).

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH.

Under these conditions, the contents of the memory location

specified by the address pins appear on the IO pins.

Product Portfolio

Power Dissipation

Speed

Product

Range

V_CCRange (V)

Operating I_CC(mA)

(ns)

Standby I_SB2(µA)

f = 1MHz

f = f_max

Min

4.5

Typ ^[3]

5.0

Max

Typ ^[3]Max Typ ^[3]Max Typ ^[3]

Max

CY62148ELL TSOP II

CY62148ELL SOIC

Ind’l

5.5

2.5

Ind’l/Auto-A

5.0

Notes

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.

2. SOIC package is available only in 55 ns speed bin.

3. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V = V

, T = 25°C.

CC(typ)

Cypress Semiconductor Corporation

Document #: 38-05442 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 28, 2007

[+] Feedback

12 3 4 5 6 7...10

中文翻译

下载PDF

与CY62148E_09相关器件

型号	品牌	获取价格	描述	数据表
CY62148E_10	CYPRESS	获取价格	4-Mbit (512 K × 8) Static RAM
CY62148E_11	CYPRESS	获取价格	4-Mbit (512 K x 8) Static RAM Automatic power-down when deselected
CY62148E_13	CYPRESS	获取价格	4-Mbit (512 K x 8) Static RAM
CY62148ELL	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148ELL-45SXI	CYPRESS	获取价格	Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62148ELL-45ZSXA	CYPRESS	获取价格	4-Mbit (512 K × 8) Static RAM
CY62148ELL-45ZSXA	ROCHESTER	获取价格	512KX8 STANDARD SRAM, 45ns, PDSO32, LEAD FREE, TSOP2-32
CY62148ELL-45ZSXAT	CYPRESS	获取价格	Standard SRAM, 512KX8, 45ns, CMOS, PDSO32
CY62148ELL-45ZSXI	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148ELL-45ZSXI	ROCHESTER	获取价格	Standard SRAM, 512KX8, 45ns, CMOS, PDSO32, LEAD FREE, TSOP2-32

与CY62148E_09相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

24
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

16
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

48
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

46

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62148E_09

CY62148E_09 数据手册

与CY62148E_09相关器件

与CY62148E_09相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62148E_09

CY62148E_09 数据手册

与CY62148E_09相关器件

与CY62148E_09相关文章

您还可以找

您在本页遇到什么问题？