Datasheet > CY62148BN_10

CY62148BN_10

更新时间： 2024-02-18 08:51:20

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	493K
描述
4-Mbit (512K x 8) Static RAM

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数据手册

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CY62148BN_10 数据手册

CY62148BN MoBL^®

4-Mbit (512K x 8) Static RAM

Features

Functional Description

■ 4.5V–5.5V operation

The CY62148BN is a high performance CMOS static RAM

organized as 512K words by 8 bits. Easy memory expansion is

provided by an active LOW Chip Enable (CE), an active LOW

Output Enable (OE), and tri-state drivers. This device has an

automatic power down feature that reduces power consumption

by more than 99% when deselected.

■ Low active power

❐ Typical active current: 2.5 mA @ f = 1 MHz

❐ Typical active current:12.5 mA @ f = fmax

■ Low standby current

To write to the device, take Chip Enable (CE) and Write Enable

(WE) inputs LOW. Data on the eight I/O pins (I/O₀through I/O₇)

is then written into the location specified on the address pins (A₀

through A₁₈).

■ Automatic power down when deselected

■ TTL-compatible inputs and outputs

■ Easy memory expansion with CE and OE features

■ CMOS for optimum speed and power

To read from the device, take Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH for

read. Under these conditions, the contents of the memory

location specified by the address pins appear on the I/O pins.

■ AvailableinstandardPb-freeandnonPb-free32-lead(450-mil)

SOIC and 32-lead TSOP II packages

The eight input/output pins (I/O₀through I/O₇) go into a

high-impedance state when the device is deselected (CE HIGH),

the outputs are disabled (OE HIGH), or a write operation is in

progress (CE LOW and WE LOW).

Logic Block Diagram

I/O

INPUT BUFFER

I/O

512K x 8

ARRAY

I/O

POWER

DOWN

COLUMN

DECODER

I/O

Cypress Semiconductor Corporation

Document Number : 001-06517 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 7, 2010

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