CY62148BNLL-70ZRC

更新时间： 2024-02-04 12:25:36

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	319K
描述
4-Mbit (512K x 8) Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62148BNLL-70ZRC 数据手册

浏览型号CY62148BNLL-70ZRC的Datasheet PDF文件第2页

浏览型号CY62148BNLL-70ZRC的Datasheet PDF文件第3页

浏览型号CY62148BNLL-70ZRC的Datasheet PDF文件第4页

浏览型号CY62148BNLL-70ZRC的Datasheet PDF文件第5页

浏览型号CY62148BNLL-70ZRC的Datasheet PDF文件第6页

浏览型号CY62148BNLL-70ZRC的Datasheet PDF文件第7页

CY62148BN MoBL^®

4-Mbit (512K x 8) Static RAM

Functional Description

Features

• High Speed

The CY62148BN is a high-performance CMOS static RAM

organized as 512K words by 8 bits. Easy memory expansion

is provided by an active LOW Chip Enable (CE), an active

LOW Output Enable (OE), and three-state drivers. This device

has an automatic power-down feature that reduces power

consumption by more than 99% when deselected.

— 70 ns

• 4.5V–5.5V operation

• Low active power

— Typical active current: 2.5 mA @ f = 1 MHz

— Typical active current:12.5 mA @ f = f_max(70 ns)

• Low standby current

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location

specified on the address pins (A₀through A₁₈).

• Automatic power-down when deselected

• TTL-compatible inputs and outputs

• Easy memory expansion with CE and OE features

• CMOS for optimum speed/power

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH for read. Under these conditions, the

contents of the memory location specified by the address pins

will appear on the I/O pins.

• Available in standard lead-free and non-lead-free

32-lead (450-mil) SOIC, 32-lead TSOP II and 32-lead

Reverse TSOP II packages

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW, and WE LOW).

Logic Block Diagram

I/O

INPUT BUFFER

I/O

512K x 8

ARRAY

I/O

POWER

DOWN

COLUMN

DECODER

I/O

Cypress Semiconductor Corporation

Document #: 001-06517 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 2, 2006

[+] Feedback

12 3 4 5 6 7...10

中文翻译

下载PDF

与CY62148BNLL-70ZRC相关器件

型号	品牌	获取价格	描述	数据表
CY62148BNLL-70ZRI	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148BNLL-70ZXC	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148BNLL-70ZXI	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148BNSL-70SXI	CYPRESS	获取价格	4-Mbit (512K x 8) Static RAM
CY62148CV25	CYPRESS	获取价格	512K x 8 MoBL Static RAM
CY62148CV25LL-55BAI	CYPRESS	获取价格	512K x 8 MoBL Static RAM
CY62148CV25LL-55BVI	CYPRESS	获取价格	512K x 8 MoBL Static RAM
CY62148CV25LL-70BAI	CYPRESS	获取价格	512K x 8 MoBL Static RAM
CY62148CV25LL-70BVI	CYPRESS	获取价格	512K x 8 MoBL Static RAM
CY62148CV25LL-70BVIT	CYPRESS	获取价格	Standard SRAM, 512KX8, 70ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36