Datasheet > CY62148DV30_11

CY62148DV30_11

更新时间： 2024-11-20 09:42:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	577K
描述
4-Mbit (512K x 8) MoBL Static RAM

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CY62148DV30_11 数据手册



CY62148DV30

4-Mbit (512K x 8) MoBL^Static RAM

Functional Description^[1]

Features

■ Temperature Ranges

❐ Industrial: –40 °C to 85 °C

The CY62148DV30 is a high-performance CMOS static RAM

organized as 512K words by 8 bits. This device features

advanced circuit design to provide ultra-low active current. This

is ideal for providing More Battery Life™ (MoBL^) in portable

applications such as cellular telephones. The device also has an

automatic power-down feature that significantly reduces power

consumption. The device can be put into standby mode reducing

power consumption when deselected (CE HIGH).The eight input

■ Very high speed: 55 ns

❐ Wide voltage range: 2.20 V – 3.60 V

■ Pin-compatible with CY62148CV25, CY62148CV30 and

CY62148CV33

■ Ultra low active power

and output pins (I/O₀through I/O₇) are placed in

high-impedance state when:

❐ Typical active current: 1.5 mA at f = 1 MHz

❐ Typical active current: 8 mA at f = f_max(55-ns speed)

■ Ultra low standby power

■ Deselected (CE HIGH)

■ Easy memory expansion with CE, and OE features

■ Automatic power-down when deselected

■ Outputs are disabled (OE HIGH)

■ When the write operation is active(CE LOW and WE LOW)

Write to the device by taking Chip Enable (CE) and Write Enable

(WE) inputs LOW. Data on the eight I/O pins (I/O₀through I/O₇)

is then written into the location specified on the address pins (A₀

through A₁₈).

■ Complementary metal oxide semiconductor (CMOS) for

optimum speed/power

■ Available in Pb-free 32-pin Small-outline integrated circuit

(SOIC package)

Read from the device by taking Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under

these conditions, the contents of the memory location specified

by the address pins will appear on the I/O pins.

Logic Block Diagram

I/O

A₀

Data in Drivers

A₁

A₂

A₃

A₄

A₅

I/O

A₆

I/O

512K x 8

ARRAY

A₇

A₈

A₉

I/O

A₁₀

A₁₁

A₁₂

I/O

POWER

DOWN

COLUMN

DECODER

I/O

Note

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document Number : 38-05341 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

• 408-943-2600

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与CY62148DV30_11相关器件

型号	品牌	获取价格	描述	数据表
CY62148DV30L	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-55BVI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-55BVXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-55SXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-55SXIT	ROCHESTER	获取价格	512KX8 STANDARD SRAM, 55ns, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62148DV30L-55SXIT	CYPRESS	获取价格	Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62148DV30L-55ZSXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-70BVI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-70BVXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-70SXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM

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