Datasheet > CY62148DV30_07

CY62148DV30_07

更新时间： 2024-11-20 04:53:27

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
10页	768K
描述
4-Mbit (512K x 8) MoBL㈢ Static RAM

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CY62148DV30_07 数据手册

CY62148DV30

4-Mbit (512K x 8) MoBL^®Static RAM

Features

Functional Description^[1]

• Temperature Ranges

The CY62148DV30 is a high-performance CMOS static RAM

organized as 512K words by 8 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

reduces power consumption. The device can be put into

standby mode reducing power consumption when deselected

(CE HIGH).The eight input and output pins (IO₀through IO₇)

are placed in a high-impedance state when:

— Industrial: –40°C to 85°C

— Automotive-A: –40°C to 85°C

• Very high speed: 55 ns

— Wide voltage range: 2.20V – 3.60V

• Pin-compatible with CY62148CV25, CY62148CV30 and

CY62148CV33

• Ultra low active power

— Typical active current: 1.5 mA @ f = 1 MHz

— Typical active current: 8 mA @ f = f_max(55-ns speed)

• Ultra low standby power

• Deselected (CE HIGH)

• Outputs are disabled (OE HIGH)

• When the write operation is active(CE LOW and WE LOW)

• Easy memory expansion with CE, and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

Write to the device by taking Chip Enable (CE) and Write

Enable (WE) inputs LOW. Data on the eight IO pins (IO₀

through IO₇) is then written into the location specified on the

address pins (A₀through A₁₈).

• Available in Pb-free and non Pb-free 36-ball VFBGA,

Pb-free 32-pin TSOPII and 32-pin SOIC packages

Read from the device by taking Chip Enable (CE) and Output

Enable (OE) LOW while forcing Write Enable (WE) HIGH.

Under these conditions, the contents of the memory location

specified by the address pins will appear on the IO pins.

Logic Block Diagram

A₀

Data in Drivers

A₁

A₂

A₃

A₄

A₅

A₆

512K x 8

ARRAY

A₇

A₈

A₉

A₁₀

A₁₁

A₁₂

POWER

DOWN

COLUMN

DECODER

Note:

1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05341 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised January 25, 2007

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与CY62148DV30_07相关器件

型号	品牌	获取价格	描述	数据表
CY62148DV30_11	CYPRESS	获取价格	4-Mbit (512K x 8) MoBL Static RAM
CY62148DV30L	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-55BVI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-55BVXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-55SXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-55SXIT	ROCHESTER	获取价格	512KX8 STANDARD SRAM, 55ns, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62148DV30L-55SXIT	CYPRESS	获取价格	Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62148DV30L-55ZSXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-70BVI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-70BVXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM

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