Datasheet > CY62148DV30L-55BVI

CY62148DV30L-55BVI

更新时间： 2024-11-20 03:55:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	185K
描述
4-Mb (512K x 8) MoBL Static RAM

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CY62148DV30

4-Mb (512K x 8) MoBL^Static RAM

Features

Functional Description^[1]

• Very high speed: 55 ns

The CY62148DV30 is a high-performance CMOS static RAMs

organized as 512K words by 8 bits. This device features

advanced circuit design to provide ultra-low active current.

— Wide voltage range: 2.20V – 3.60V

• Pin-compatible with CY62148CV25, CY62148CV30 and

CY62148CV33

• Ultra low active power

This is ideal for providing More Battery Life™ (MoBL^) in

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

reduces power consumption. The device can be put into

standby mode reducing power consumption when deselected

(CE HIGH).

— Typical active current: 1.5 mA @ f = 1 MHz

— Typical active current: 8 mA @ f = f_max(55-ns speed)

• Ultra low standby power

• Easy memory expansion with CE, and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location

specified on the address pins (A₀through A₁₈).

• Packages offered: 36-ball BGA, 32-pin TSOPII and

32-pin SOIC

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW and WE LOW).

Logic Block Diagram

I/O

Data in Drivers

512K x 8

ARRAY

A₁₂

POWER

DOWN

COLUMN

DECODER

I/O

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05341 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised February 10, 2004

12 3 4 5 6 7...11

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与CY62148DV30L-55BVI相关器件

型号	品牌	获取价格	描述	数据表
CY62148DV30L-55BVXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-55SXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-55SXIT	ROCHESTER	获取价格	512KX8 STANDARD SRAM, 55ns, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62148DV30L-55SXIT	CYPRESS	获取价格	Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62148DV30L-55ZSXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-70BVI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-70BVXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-70SXI	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30L-70SXI	ROCHESTER	获取价格	512KX8 STANDARD SRAM, 70ns, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62148DV30L-70SXIT	CYPRESS	获取价格	暂无描述

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