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CY62148CV30LL-55BAIT

更新时间： 2024-11-20 13:07:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
13页 274K
描述
Standard SRAM, 512KX8, 55ns, CMOS, PBGA36, 7 X 8.50 MM, 1.20 MM HEIGHT, FPBGA-36

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CY62148CV30LL-55BAIT 技术参数

生命周期：Obsolete零件包装代码：BGA
包装说明：7 X 8.50 MM, 1.20 MM HEIGHT, FPBGA-36针数：36
Reach Compliance Code：unknownECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.65
最长访问时间：55 nsJESD-30 代码：R-PBGA-B36
长度：8.5 mm内存密度：4194304 bit
内存集成电路类型：STANDARD SRAM内存宽度：8
功能数量：1端子数量：36
字数：524288 words字数代码：512000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX8
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH
并行/串行：PARALLEL认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.3 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：BALL
端子节距：0.75 mm端子位置：BOTTOM
宽度：7 mmBase Number Matches：1

CY62148CV30LL-55BAIT 数据手册

 浏览型号CY62148CV30LL-55BAIT的Datasheet PDF文件第2页浏览型号CY62148CV30LL-55BAIT的Datasheet PDF文件第3页浏览型号CY62148CV30LL-55BAIT的Datasheet PDF文件第4页浏览型号CY62148CV30LL-55BAIT的Datasheet PDF文件第5页浏览型号CY62148CV30LL-55BAIT的Datasheet PDF文件第6页浏览型号CY62148CV30LL-55BAIT的Datasheet PDF文件第7页 
CY62148CV25/30/33  
MoBL™  
512K x 8 MoBL Static RAM  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life™ (MoBL™) in por-  
table applications such as cellular telephones. The device also  
has an automatic power-down feature that significantly reduc-  
es power consumption by 80% when addresses are not tog-  
gling. The device can be put into standby mode when dese-  
lected (CE HIGH).  
Features  
• High Speed  
— 55 ns and 70 ns availability  
• Low voltage range:  
— CY62148CV25: 2.2V–2.7V  
— CY62148CV30: 2.7V–3.3V  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O0 through I/O7) is then written into the location speci-  
fied on the address pins (A0 through A18).  
— CY62148CV33: 3.0V–3.6V  
• Pin compatible with CY62148V  
• Ultra low active power  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
— Typical active current: 1.5 mA @ f = 1MHz  
— Typicalactivecurrent:5.5mA@f=fmax (70nsspeed)  
• Low standby power  
• Easy memory expansion with CE and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
The eight input/output pins (I/O0 through I/O7) are placed in a  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW and WE LOW).  
Functional Description  
The CY62148CV25/30/33 are available in a 36-ball FBGA  
package.  
The CY62148CV25/30/33 are high-performance CMOS static  
RAMs organized as 512K words by 8 bits. This device features  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
Data in Drivers  
A
0
A
1
A
2
A
3
A
4
A
3
4
5
6
512K x 8  
ARRAY  
5
A
6
A
A
A
7
8
9
POWER  
DOWN  
COLUMN  
DECODER  
CE  
I/O  
WE  
7
OE  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05035 Rev. *A  
Revised September 7, 2001  
1234567...13

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 		Standard SRAM, 512KX8, 55ns, CMOS, PBGA36, 7 X 8.50 MM, 1.20 MM HEIGHT, FPBGA-36
CY62148CV33LL-55BVI CYPRESS

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 		512K x 8 MoBL Static RAM
CY62148CV33LL-55BVIT CYPRESS

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CY62148CV33LL-70BAIT CYPRESS

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