Datasheet > CY62148CV33

CY62148CV33

更新时间： 2024-01-09 20:09:21

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	274K
描述
512K x 8 MoBL Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62148CV33 数据手册

CY62148CV25/30/33

MoBL™

512K x 8 MoBL Static RAM

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL™) in por-

table applications such as cellular telephones. The device also

has an automatic power-down feature that significantly reduc-

es power consumption by 80% when addresses are not tog-

gling. The device can be put into standby mode when dese-

lected (CE HIGH).

Features

• High Speed

— 55 ns and 70 ns availability

• Low voltage range:

— CY62148CV25: 2.2V–2.7V

— CY62148CV30: 2.7V–3.3V

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O

pins (I/O₀through I/O₇) is then written into the location speci-

fied on the address pins (A₀through A₁₈).

— CY62148CV33: 3.0V–3.6V

• Pin compatible with CY62148V

• Ultra low active power

Reading from the device is accomplished by taking Chip En-

able (CE) and Output Enable (OE) LOW while forcing Write

Enable (WE) HIGH. Under these conditions, the contents of

the memory location specified by the address pins will appear

on the I/O pins.

— Typical active current: 1.5 mA @ f = 1MHz

— Typicalactivecurrent:5.5mA@f=f_max(70nsspeed)

• Low standby power

• Easy memory expansion with CE and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

The eight input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when the device is deselected (CE

HIGH), the outputs are disabled (OE HIGH), or during a write

operation (CE LOW and WE LOW).

Functional Description

The CY62148CV25/30/33 are available in a 36-ball FBGA

package.

The CY62148CV25/30/33 are high-performance CMOS static

RAMs organized as 512K words by 8 bits. This device features

Logic Block Diagram

I/O

Data in Drivers

512K x 8

ARRAY

POWER

DOWN

COLUMN

DECODER

I/O

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05035 Rev. *A

Revised September 7, 2001

12 3 4 5 6 7...13

中文翻译

下载PDF

与CY62148CV33相关器件

型号	品牌	获取价格	描述	数据表
CY62148CV33LL-55BAI	CYPRESS	获取价格	512K x 8 MoBL Static RAM
CY62148CV33LL-55BAIT	CYPRESS	获取价格	Standard SRAM, 512KX8, 55ns, CMOS, PBGA36, 7 X 8.50 MM, 1.20 MM HEIGHT, FPBGA-36
CY62148CV33LL-55BVI	CYPRESS	获取价格	512K x 8 MoBL Static RAM
CY62148CV33LL-55BVIT	CYPRESS	获取价格	Standard SRAM, 512KX8, 55ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36
CY62148CV33LL-70BAI	CYPRESS	获取价格	512K x 8 MoBL Static RAM
CY62148CV33LL-70BAIT	CYPRESS	获取价格	Standard SRAM, 512KX8, 70ns, CMOS, PBGA36, 7 X 8.50 MM, 1.20 MM HEIGHT, FPBGA-36
CY62148CV33LL-70BVI	CYPRESS	获取价格	512K x 8 MoBL Static RAM
CY62148CV33LL-70BVIT	CYPRESS	获取价格	Standard SRAM, 512KX8, 70ns, CMOS, PBGA36, 6 X 8 MM, 1 MM HEIGHT, VFBGA-36
CY62148DV30	CYPRESS	获取价格	4-Mb (512K x 8) MoBL Static RAM
CY62148DV30_07	CYPRESS	获取价格	4-Mbit (512K x 8) MoBL㈢ Static RAM

与CY62148CV33相关文章

BSS138LT3G：一款高效能N沟道MOSFET的全面解析
2024-07-04

2
解读EGP10B二极管资料手册：产品特性、参数分析
2024-07-04

2
RT9164AGG手册资料详解：引脚信息、设计指南
2024-07-04

2
2SA1037KPT资料详解：产品特性、电气参数、设计指南
2024-07-04

2

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62148CV33

CY62148CV33 数据手册

与CY62148CV33相关器件

与CY62148CV33相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62148CV33

CY62148CV33 数据手册

与CY62148CV33相关器件

与CY62148CV33相关文章

您还可以找

您在本页遇到什么问题？