5秒后页面跳转
捷配首页

Datasheet > CY62136V18LL-70BAI
CY62136V18LL-70BAI PDF预览

CY62136V18LL-70BAI

更新时间： 2024-11-04 23:45:07
品牌 Logo 应用领域
其他 - ETC 内存集成电路静态存储器
页数 文件大小 规格书
10页 253K
描述
x16 SRAM

阅读下载

中文翻译

获取价格

CY62136V18LL-70BAI 数据手册

 浏览型号CY62136V18LL-70BAI的Datasheet PDF文件第2页浏览型号CY62136V18LL-70BAI的Datasheet PDF文件第3页浏览型号CY62136V18LL-70BAI的Datasheet PDF文件第4页浏览型号CY62136V18LL-70BAI的Datasheet PDF文件第5页浏览型号CY62136V18LL-70BAI的Datasheet PDF文件第6页浏览型号CY62136V18LL-70BAI的Datasheet PDF文件第7页 
CY62136V MoBL™  
CY62136V18 MoBL2™  
128K x 16 Static RAM  
put/output pins (I/O through I/O ) are placed in a high-im-  
Features  
0
15  
pedance state when: deselected (CE HIGH), outputs are dis-  
abled (OE HIGH), BHE and BLE are disabled (BHE, BLE  
HIGH), or during a write operation (CE LOW, and WE LOW).  
• Low voltage range:  
CY62136V18: 1.65V 1.95V  
—
−
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
— CY62136V: 2.7V 3.6V  
−
• Ultra-low active, standby power  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
0
7
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
written into the location specified on the address pins (A  
0
through A ). If Byte High Enable (BHE) is LOW, then data  
16  
from I/O pins (I/O through I/O ) is written into the location  
8
15  
specified on the address pins (A through A ).  
0
16  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
Functional Description  
The CY62136V and CY62136V18 are high-performance  
CMOS static RAMs organized as 131,072 words by 16 bits.  
This device features advanced circuit design to provide ul-  
tra-low active current. This is ideal for providing More Battery  
Life™ (MoBL™) in portable applications such as cellular tele-  
phones. The device also has an automatic power-down fea-  
ture that significantly reduces power consumption by 99%  
when addresses are not toggling. The device can also be put  
into standby mode when deselected (CE HIGH). The in-  
will appear on I/O to I/O . If Byte High Enable (BHE) is LOW,  
0
7
then data from memory will appear on I/O to I/O . See the  
8
15  
Truth Table at the back of this data sheet for a complete de-  
scription of read and write modes.  
The CY62136V and CY62136V18 are available in 48-ball  
FBGA and standard 44-pin TSOP Type II (forward pinout)  
packaging.  
Logic Block Diagram  
Pin Configurations  
TSOP II (Forward)  
Top View  
44  
1
A
4
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
DATA IN DRIVERS  
A
A
2
7
OE  
A
1
BHE  
BLE  
I/O  
I/O  
I/O  
A
0
CE  
A9  
A7  
I/O  
7
0
15  
37  
36  
35  
34  
33  
I/O  
I/O  
8
1
2
14  
13  
12  
A6  
A3  
A2  
A1  
A0  
128K x 16  
9
10  
11  
12  
13  
I/O  
V
SS  
RAM Array  
1024 X 2048  
I/O  
I/O0–I/O7  
3
CC  
V
SS  
V
V
I/O8–I/O15  
CC  
I/O  
32  
I/O  
I/O  
4
5
6
7
11  
10  
I/O  
I/O  
I/O  
31  
30  
29  
28  
14  
15  
16  
I/O  
I/O  
9
8
WE 17  
NC  
18  
27  
26  
25  
A
A
8
16  
19  
A
A
9
COLUMN DECODER  
15  
A
20  
21  
22  
A
11  
14  
10  
A
A
12  
24  
23  
13  
A
NC  
BHE  
WE  
CE  
OE  
62136V–2  
BLE  
62136V–1  
More Battery Life and MoBL are trademarks of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
January 20, 2000  
1234567...10

中文翻译

下载PDF

与CY62136V18LL-70BAI相关器件

型号 品牌 获取价格 描述 数据表
CY62136VLL CYPRESS

获取价格

 		128K x 16 Static RAM
CY62136VLL-55BAI CYPRESS

获取价格

 		2-Mbit (128K x 16) Static RAM
CY62136VLL-55ZI CYPRESS

获取价格

 		128K x 16 Static RAM
CY62136VLL-55ZIT CYPRESS

获取价格

 		Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, TSOP2-44
CY62136VLL-55ZSI CYPRESS

获取价格

 		2-Mbit (128K x 16) Static RAM
CY62136VLL-55ZXI CYPRESS

获取价格

 		2-Mbit (128K x 16) Static RAM
CY62136VLL-55ZXIT CYPRESS

获取价格

 		Standard SRAM, 128KX16, 55ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62136VLL-70BAI CYPRESS

获取价格

 		128K x 16 Static RAM
CY62136VLL-70BAIT CYPRESS

获取价格

 		Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
CY62136VLL-70ZI CYPRESS

获取价格

 		128K x 16 Static RAM

与CY62136V18LL-70BAI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证