Datasheet > CY62137CV

CY62137CV

更新时间： 2024-11-04 22:56:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	229K
描述
2M (128K x 16) Static RAM

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CY62137CV 数据手册

CY62137CV25/30/33 MoBL

CY62137CV MoBL

2M (128K x 16) Static RAM

Life™ (MoBL®) in portable applications such as cellular tele-

phones. The devices also has an automatic power-down fea-

ture that significantly reduces power consumption by 80%

when addresses are not toggling. The device can also be put

into standby mode reducing power consumption by more than

99% when deselected (CE HIGH or both BLE and BHE are

HIGH). The input/output pins (I/O₀through I/O₁₅) are placed

in a high-impedance state when: deselected (CE HIGH), out-

puts are disabled (OE HIGH), both Byte High Enable and Byte

Low Enable are disabled (BHE, BLE HIGH), or during a write

operation (CE LOW, and WE LOW).

Features

• Very high speed: 55 ns and 70 ns

• Voltage range:

— CY62137CV25: 2.2V–2.7V

— CY62137CV30: 2.7V–3.3V

— CY62137CV33: 3.0V–3.6V

— CY62137CV: 2.7V–3.6V

• Pin-compatible with the CY62137V

• Ultra-low active power

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀

through A₁₆). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₆).

— Typical active current: 1.5 mA @ f = 1 MHz

— Typical active current: 5.5 mA @ f = f_max(70-ns

speed)

• Low and ultra-low standby power

• Easy memory expansion with CE and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the truth table at the back of this data sheet for a complete

description of read and write modes.

• Packages offered in a 48-ball FBGA

Functional Description^[1]

The CY62137CV25/30/33 and CY62137CV are high-perfor-

mance CMOS static RAMs organized as 128K words by 16

bits. These devices feature advanced circuit design to provide

ultra-low active current. This is ideal for providing More Battery

Logic Block Diagram

DATA IN DRIVERS

128K x 16

RAM Array

I/O – I/O

2048 x 1024

I/O – I/O

COLUMN DECODER

BHE

BLE

Power-down

Circuit

BHE

BLE

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05201 Rev. *D

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised September 20, 2002

12 3 4 5 6 7...13

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与CY62137CV相关器件

型号	品牌	获取价格	描述	数据表
CY62137CV18	CYPRESS	获取价格	128K x 16 Static RAM
CY62137CV18_02	CYPRESS	获取价格	128K x 16 Static RAM
CY62137CV18LL-55BAI	ROCHESTER	获取价格	128KX16 STANDARD SRAM, 55ns, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
CY62137CV18LL-55BAI	CYPRESS	获取价格	128K x 16 Static RAM
CY62137CV18LL-55BAIT	CYPRESS	获取价格	Standard SRAM, 128KX16, 55ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
CY62137CV18LL-55BVI	CYPRESS	获取价格	128K x 16 Static RAM
CY62137CV18LL-70BAI	CYPRESS	获取价格	128K x 16 Static RAM
CY62137CV18LL-70BAIT	ROCHESTER	获取价格	128KX16 STANDARD SRAM, 70ns, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
CY62137CV18LL-70BVI	CYPRESS	获取价格	128K x 16 Static RAM
CY62137CV25	CYPRESS	获取价格	2M (128K x 16) Static RAM

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