Datasheet > CY62137CV18_02

CY62137CV18_02

更新时间： 2024-11-05 04:53:23

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
11页	246K
描述
128K x 16 Static RAM

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CY62137CV18_02 数据手册

CY62137CV18 MoBL2™

128K x 16 Static RAM

reduces power consumption by 99% when addresses are not

toggling. The device can also be put into standby mode when

deselected (CE HIGH or both BLE and BHE are HIGH). The

input/output pins (I/O₀through I/O₁₅) are placed in a

high-impedance state when: deselected (CE HIGH), outputs

are disabled (OE HIGH), both Byte High Enable and Byte Low

Enable are disabled (BHE, BLE HIGH), or during a write

operation (CE LOW, and WE LOW).

Features

• High speed

— 55 ns and 70 ns availability

• Low voltage range:

— 1.65V−1.95V

• Pin-compatible with CY62137BV18

• Ultra-low active power

— Typical Active Current: 0.5 mA @ f = 1 MHz

Writing to the device is accomplished by taking Chip Enable

(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable

(BLE) is LOW, then data from I/O pins (I/O₀through I/O₇), is

written into the location specified on the address pins (A₀

through A₁₆). If Byte High Enable (BHE) is LOW, then data

from I/O pins (I/O₈through I/O₁₅) is written into the location

specified on the address pins (A₀through A₁₆).

— Typical Active Current: 1.5 mA @ f = f_max(70 ns

speed)

• Low standby power

• Easy memory expansion with CE and OE features

• Automatic power-down when deselected

• CMOS for optimum speed/power

Reading from the device is accomplished by taking Chip

Enable (CE) and Output Enable (OE) LOW while forcing the

Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,

then data from the memory location specified by the address

pins will appear on I/O₀to I/O₇. If Byte High Enable (BHE) is

LOW, then data from memory will appear on I/O₈to I/O₁₅. See

the Truth Table at the back of this data sheet for a complete

description of read and write modes.

Functional Description

The CY62137CV18 is a high-performance CMOS static RAM

organized as 128K words by 16 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL ) in

portable applications such as cellular telephones. The device

also has an automatic power-down feature that significantly

The CY62137CV18 is available in a 48-ball FBGA package.

Logic Block Diagram

DATA IN DRIVERS

128K x 16

RAM Array

I/O –I/O

2048 X 1024

I/O –I/O

COLUMN DECODER

BHE

BLE

Power -Down

Circuit

BHE

BLE

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-05017 Rev. *C

Revised August 28, 2002

12 3 4 5 6 7...11

中文翻译

下载PDF

与CY62137CV18_02相关器件

型号	品牌	获取价格	描述	数据表
CY62137CV18LL-55BAI	ROCHESTER	获取价格	128KX16 STANDARD SRAM, 55ns, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
CY62137CV18LL-55BAI	CYPRESS	获取价格	128K x 16 Static RAM
CY62137CV18LL-55BAIT	CYPRESS	获取价格	Standard SRAM, 128KX16, 55ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
CY62137CV18LL-55BVI	CYPRESS	获取价格	128K x 16 Static RAM
CY62137CV18LL-70BAI	CYPRESS	获取价格	128K x 16 Static RAM
CY62137CV18LL-70BAIT	ROCHESTER	获取价格	128KX16 STANDARD SRAM, 70ns, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
CY62137CV18LL-70BVI	CYPRESS	获取价格	128K x 16 Static RAM
CY62137CV25	CYPRESS	获取价格	2M (128K x 16) Static RAM
CY62137CV25_06	CYPRESS	获取价格	2M (128K x 16) Static RAM
CY62137CV25LL-55BAI	CYPRESS	获取价格	2M (128K x 16) Static RAM

与CY62137CV18_02相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

14
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

10
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

36
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62137CV18_02

CY62137CV18_02 数据手册

与CY62137CV18_02相关器件

与CY62137CV18_02相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY62137CV18_02

CY62137CV18_02 数据手册

与CY62137CV18_02相关器件

与CY62137CV18_02相关文章

您还可以找

您在本页遇到什么问题？