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CY62137CV30LL-55BAI PDF预览

CY62137CV30LL-55BAI

更新时间： 2024-11-08 22:07:51
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
13页 229K
描述
2M (128K x 16) Static RAM

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中文翻译

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CY62137CV30LL-55BAI 技术参数

是否Rohs认证：不符合生命周期：Obsolete
零件包装代码：BGA包装说明：7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
针数：48Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.77
Is Samacsys：N最长访问时间：55 ns
I/O 类型：COMMONJESD-30 代码：S-PBGA-B48
JESD-609代码：e0长度：7 mm
内存密度：2097152 bit内存集成电路类型：STANDARD SRAM
内存宽度：16功能数量：1
端子数量：48字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：128KX16输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：TFBGA
封装等效代码：BGA48,6X8,30封装形状：SQUARE
封装形式：GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行：PARALLEL
电源：3 V认证状态：Not Qualified
座面最大高度：1.2 mm最大待机电流：0.000006 A
最小待机电流：1.5 V子类别：SRAMs
最大压摆率：0.015 mA最大供电电压 (Vsup)：3.3 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.75 mm
端子位置：BOTTOM宽度：7 mm
Base Number Matches：1

CY62137CV30LL-55BAI 数据手册

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®
®
CY62137CV25/30/33 MoBL  
CY62137CV MoBL  
2M (128K x 16) Static RAM  
Life™ (MoBL®) in portable applications such as cellular tele-  
phones. The devices also has an automatic power-down fea-  
ture that significantly reduces power consumption by 80%  
when addresses are not toggling. The device can also be put  
into standby mode reducing power consumption by more than  
99% when deselected (CE HIGH or both BLE and BHE are  
HIGH). The input/output pins (I/O0 through I/O15) are placed  
in a high-impedance state when: deselected (CE HIGH), out-  
puts are disabled (OE HIGH), both Byte High Enable and Byte  
Low Enable are disabled (BHE, BLE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
Features  
• Very high speed: 55 ns and 70 ns  
• Voltage range:  
— CY62137CV25: 2.2V–2.7V  
— CY62137CV30: 2.7V–3.3V  
— CY62137CV33: 3.0V–3.6V  
— CY62137CV: 2.7V–3.6V  
• Pin-compatible with the CY62137V  
• Ultra-low active power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).  
— Typical active current: 1.5 mA @ f = 1 MHz  
— Typical active current: 5.5 mA @ f = fmax (70-ns  
speed)  
• Low and ultra-low standby power  
• Easy memory expansion with CE and OE features  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the truth table at the back of this data sheet for a complete  
description of read and write modes.  
• Packages offered in a 48-ball FBGA  
Functional Description[1]  
The CY62137CV25/30/33 and CY62137CV are high-perfor-  
mance CMOS static RAMs organized as 128K words by 16  
bits. These devices feature advanced circuit design to provide  
ultra-low active current. This is ideal for providing More Battery  
Logic Block Diagram  
DATA IN DRIVERS  
10  
A
10  
A
9
A
8
7
6
A
A
A
A
A
128K x 16  
5
4
RAM Array  
I/O – I/O  
0
7
2048 x 1024  
3
2
I/O – I/O  
A
8
15  
A
A
1
0
COLUMN DECODER  
BHE  
WE  
CE  
OE  
BLE  
CE  
Power-down  
Circuit  
BHE  
BLE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05201 Rev. *D  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Revised September 20, 2002  
1234567...13

中文翻译

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与CY62137CV30LL-55BAI相关器件

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CY62137CV30LL-55BVI CYPRESS

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 		2M (128K x 16) Static RAM
CY62137CV30LL-55BVIT CYPRESS

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 		Standard SRAM, 128KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48
CY62137CV30LL-55BVIT ROCHESTER

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 		128KX16 STANDARD SRAM, 55ns, PBGA48, 6 X 8 MM, 1 MM HEIGHT, FBGA-48
CY62137CV30LL-55BVXI CYPRESS

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 		2-Mbit (128K x 16) Static RAM
CY62137CV30LL-55BVXIT CYPRESS

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 		Standard SRAM, 128KX16, 55ns, CMOS, PBGA48, 6 X 8 MM, 1 MM HEIGHT, LEAD FREE, FBGA-48
CY62137CV30LL-70BAE CYPRESS

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 		2-Mbit (128K x 16) Static RAM
CY62137CV30LL-70BAET CYPRESS

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 		暂无描述
CY62137CV30LL-70BAI CYPRESS

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 		2M (128K x 16) Static RAM
CY62137CV30LL-70BAIT CYPRESS

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 		Standard SRAM, 128KX16, 70ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
CY62137CV30LL-70BAIT ROCHESTER

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 		128KX16 STANDARD SRAM, 70ns, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48

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