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CY62136VLL-55ZI

更新时间： 2024-10-01 21:55:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 221K
描述
128K x 16 Static RAM

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CY62136VLL-55ZI 数据手册

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CY62136V MoBL™  
128K x 16 Static RAM  
HIGH), outputs are disabled (OE HIGH), BHE and BLE are  
disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
Features  
• Low voltage range:  
— CY62136V: 2.7V-3.6V  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).  
• Ultra-low active, standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Functional Description  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the Write  
Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
will appear on I/O0 to I/O7. If Byte High Enable (BHE) is LOW,  
then data from memory will appear on I/O8 to I/O15. See the  
Truth Table at the back of this data sheet for a complete de-  
scription of read and write modes.  
The CY62136V is a high-performance CMOS static RAM or-  
ganized as 131,072 words by 16 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life™ (MoBL™) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that significantly reduces  
power consumption by 99% when addresses are not toggling.  
The device can also be put into standby mode when deselect-  
ed (CE HIGH). The input/output pins (I/O0 through I/O15) are  
placed in a high-impedance state when: deselected (CE  
The CY62136V is available in 48-ball FBGA and standard  
44-pin TSOP Type II (forward pinout) packaging.  
Logic Block Diagram  
Pin Configurations  
TSOP II (Forward)  
Top View  
44  
1
A
4
A
5
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
DATA IN DRIVERS  
A
A
2
7
OE  
A
1
A
8
BHE  
BLE  
I/O  
A
0
A
7
CE  
A
I/O  
6
7
0
15  
37  
36  
35  
34  
33  
A
I/O  
I/O  
8
I/O  
I/O  
5
1
2
14  
13  
12  
128K x 16  
9
A
4
10  
11  
12  
13  
I/O  
V
SS  
RAM Array  
1024 X 2048  
I/O –I/O  
I/O  
3
CC  
0
7
A
3
V
SS  
A
A
V
V
2
I/O –I/O  
CC  
8
15  
32  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
1
0
31  
30  
29  
28  
I/O  
I/O  
I/O  
14  
15  
16  
A
I/O  
I/O  
9
8
WE 17  
NC  
18  
27  
26  
25  
A
A
8
16  
19  
A
A
9
COLUMN DECODER  
15  
A
A
A
20  
21  
22  
A
11  
14  
10  
A
24  
23  
13  
NC  
12  
BHE  
WE  
CE  
OE  
BLE  
MoBL and More Battery Life are trademarks of Cypress Semiconductor Corporation.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-05087 Rev. **  
Revised September 5, 2000  
1234567...12

中文翻译

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CY62136VLL-55ZI 替代型号

型号 品牌 替代类型 描述 数据表
CY62137VLL-55ZI CYPRESS

完全替代

 2-Mbit (128K x 16) Static RAM
CY62136VNLL-55ZXI CYPRESS

类似代替

 2-Mbit (128K x 16) Static RAM
CY62136VNLL-55ZSXA CYPRESS

功能相似

 2-Mbit (128K x 16) Static RAM

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