5秒后页面跳转
CY62136VNLL-70ZXI PDF预览

CY62136VNLL-70ZXI

更新时间: 2024-10-02 03:19:35
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 573K
描述
2-Mbit (128K x 16) Static RAM

CY62136VNLL-70ZXI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:LEAD FREE, TSOP2-44
针数:44Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.73最长访问时间:70 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G44
JESD-609代码:e4长度:18.415 mm
内存密度:2097152 bit内存集成电路类型:STANDARD SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:44
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP2封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:3/3.3 V认证状态:Not Qualified
座面最大高度:1.194 mm最大待机电流:0.0000075 A
最小待机电流:1 V子类别:SRAMs
最大压摆率:0.015 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.8 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:10.16 mmBase Number Matches:1

CY62136VNLL-70ZXI 数据手册

 浏览型号CY62136VNLL-70ZXI的Datasheet PDF文件第2页浏览型号CY62136VNLL-70ZXI的Datasheet PDF文件第3页浏览型号CY62136VNLL-70ZXI的Datasheet PDF文件第4页浏览型号CY62136VNLL-70ZXI的Datasheet PDF文件第5页浏览型号CY62136VNLL-70ZXI的Datasheet PDF文件第6页浏览型号CY62136VNLL-70ZXI的Datasheet PDF文件第7页 
CY62136VN MoBL®  
2-Mbit (128K x 16) Static RAM  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption by 99% when addresses are not  
toggling. The device can also be put into standby mode when  
deselected (CE HIGH). The input/output pins (I/O0 through  
I/O15) are placed in a high-impedance state when: deselected  
(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
Features  
• Temperature Ranges  
— Industrial: –40°C to 85°C  
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• High speed: 55 ns  
• Wide voltage range: 2.7V–3.6V  
• Ultra-low active, standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is  
written into the location specified on the address pins (A0  
through A16). If Byte High Enable (BHE) is LOW, then data  
from I/O pins (I/O8 through I/O15) is written into the location  
specified on the address pins (A0 through A16).  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
pins will appear on I/O0 to I/O7. If Byte High Enable (BHE) is  
LOW, then data from memory will appear on I/O8 to I/O15. See  
the Truth Table at the back of this data sheet for a complete  
description of read and write modes.  
• Available in standard Pb-free 44-pin TSOP Type II,  
Pb-free and non Pb-free 48-ball FBGA packages  
Functional Description[1]  
The CY62136VN is a high-performance CMOS static RAM  
organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
This is ideal for providing More Battery Life(MoBL®) in  
PinConfigurations[3]  
Logic Block Diagram  
TSOP II (Forward)  
Top View  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
44  
1
A
A
A
A
A
CE  
I/O  
I/O  
I/O  
A
A
A
4
3
2
1
0
5
6
43  
42  
41  
40  
39  
38  
2
3
4
5
6
7
OE  
BHE  
BLE  
I/O  
I/O  
I/O  
I/O  
V
V
I/O  
I/O  
I/O  
I/O  
NC  
A
A
A
A
128K x 16  
RAM Array  
I/O0 – I/O7  
I/O8 – I/O15  
7
0
15  
37  
36  
35  
34  
33  
8
1
2
14  
13  
12  
9
10  
11  
12  
13  
I/O  
V
3
SS  
CC  
V
SS  
CC  
32  
I/O  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
31  
30  
29  
28  
14  
15  
16  
17  
18  
19  
20  
21  
22  
9
8
COLUMN DECODER  
WE  
27  
26  
25  
A
8
9
10  
11  
16  
15  
14  
BHE  
WE  
CE  
OE  
BLE  
A
A
A
24  
23  
13  
A
NC  
12  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 001-06510 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 3, 2006  
[+] Feedback  

CY62136VNLL-70ZXI 替代型号

型号 品牌 替代类型 描述 数据表
CY62136VLL-70ZSXE CYPRESS

功能相似

2-Mbit (128K x 16) Static RAM
M68AW128ML70ND6 STMICROELECTRONICS

功能相似

2 Mbit (128K x16) 3.0V Asynchronous SRAM
CY62136VLL-70ZI CYPRESS

功能相似

128K x 16 Static RAM

与CY62136VNLL-70ZXI相关器件

型号 品牌 获取价格 描述 数据表
CY62136VNLL-70ZXIT CYPRESS

获取价格

Standard SRAM, 128KX16, 70ns, CMOS, PDSO44, LEAD FREE, TSOP2-44
CY62136VSL-55ZSI CYPRESS

获取价格

2-Mbit (128K x 16) Static RAM
CY62136VSL-70ZSI CYPRESS

获取价格

2-Mbit (128K x 16) Static RAM
CY62137BV18LL-70BAI ETC

获取价格

x16 SRAM
CY62137CV CYPRESS

获取价格

2M (128K x 16) Static RAM
CY62137CV18 CYPRESS

获取价格

128K x 16 Static RAM
CY62137CV18_02 CYPRESS

获取价格

128K x 16 Static RAM
CY62137CV18LL-55BAI ROCHESTER

获取价格

128KX16 STANDARD SRAM, 55ns, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48
CY62137CV18LL-55BAI CYPRESS

获取价格

128K x 16 Static RAM
CY62137CV18LL-55BAIT CYPRESS

获取价格

Standard SRAM, 128KX16, 55ns, CMOS, PBGA48, 7 X 7 MM, 1.20 MM HEIGHT, FBGA-48