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CY62136FV30LL-45BVXI PDF预览

CY62136FV30LL-45BVXI

更新时间: 2024-11-16 02:52:15
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
12页 509K
描述
2-Mbit (128K x 16) Static RAM

CY62136FV30LL-45BVXI 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:BGA
包装说明:VFBGA, BGA48,6X8,30针数:48
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41Factory Lead Time:1 week
风险等级:5.51最长访问时间:45 ns
I/O 类型:COMMONJESD-30 代码:R-PBGA-B48
JESD-609代码:e1长度:8 mm
内存密度:2097152 bit内存集成电路类型:STANDARD SRAM
内存宽度:16湿度敏感等级:3
功能数量:1端子数量:48
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:VFBGA封装等效代码:BGA48,6X8,30
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:2.5/3.3 V认证状态:Not Qualified
座面最大高度:1 mm最大待机电流:0.000004 A
最小待机电流:1.5 V子类别:SRAMs
最大压摆率:0.025 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.2 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:0.75 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:30
宽度:6 mmBase Number Matches:1

CY62136FV30LL-45BVXI 数据手册

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CY62136FV30 MoBL®  
2-Mbit (128K x 16) Static RAM  
automatic power down feature that significantly reduces power  
consumption by 90% when addresses are not toggling. Placing  
the device into standby mode reduces power consumption by  
more than 99% when deselected (CE HIGH). The input and  
output pins (IO0 through IO15) are placed in a high impedance  
state when:  
Features  
Very high speed: 45 ns  
Temperature ranges  
Industrial: –40°C to +85°C  
Automotive: –40°C to +125°C  
Deselected (CE HIGH)  
Wide voltage range: 2.20V–3.60V  
Outputs are disabled (OE HIGH)  
Pin compatible with CY62136V, CY62136CV30/CV33, and  
CY62136EV30  
Both Byte High Enable and Byte Low Enable are disabled  
(BHE, BLE HIGH)  
Ultra low standby power  
Write operation is active (CE LOW and WE LOW)  
Typical standby current: 1µA  
Maximum standby current: 5 µA (Industrial)  
Ultra low active power  
Write to the device by taking Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from IO pins (IO0 through IO7) is written into the location  
specified on the address pins (A0 through A16). If Byte High  
Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)  
Easy memory expansion with CE, and OE features  
Enable (BHE) is LOW, then data from IO pins (IO8 through IO15  
)
Automatic power down when deselected  
CMOS for optimum speed and power  
is written into the location specified on the address pins (A0  
through A16).  
Available in Pb-free 48-ball VFBGA and 44-pin TSOP II  
packages  
Read from the device by taking Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appears on IO0 to IO7. If  
Byte High Enable (BHE) is LOW, then data from memory  
appears on IO8 to IO15. See the “Truth Table” on page 9 for a  
complete description of read and write modes.  
Functional Description  
The CY62136FV30 is a high performance CMOS static RAM  
organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
For best practice recommendations, refer to the Cypress  
application note AN1064, SRAM System Guidelines.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
128K x 16  
RAM Array  
IO0–IO7  
IO8–IO15  
A2  
A1  
A0  
BHE  
WE  
CE  
COLUMN DECODER  
OE  
BLE  
Cypress Semiconductor Corporation  
Document Number: 001-08402 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 03, 2007  

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