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CY62136FV30LL-55ZSXE PDF预览

CY62136FV30LL-55ZSXE

更新时间： 2024-10-03 14:56:11
品牌 Logo 应用领域
英飞凌 - INFINEON 静态存储器
页数 文件大小 规格书
18页 510K
描述
Asynchronous SRAM

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CY62136FV30LL-55ZSXE 数据手册

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CY62136FV30 MoBL®  
2-Mbit (128 K × 16) Static RAM  
2-Mbit (128  
K × 16) Static RAM  
Features  
Functional Description  
■ Very high speed: 45 ns  
The CY62136FV30 is a high performance CMOS static RAM  
organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra low active current. This  
is ideal for providing More Battery Life™ (MoBL®) in portable  
applications such as cellular telephones. The device also has an  
automatic power down feature that significantly reduces power  
consumption by 90 percent when addresses are not toggling.  
Placing the device into standby mode reduces power  
consumption by more than 99 percent when deselected (CE  
HIGH). The input and output pins (I/O0 through I/O15) are placed  
in a high impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), both Byte High  
Enable and Byte Low Enable are disabled (BHE, BLE HIGH) or  
during a write operation (CE LOW and WE LOW).  
■ Temperature ranges  
❐ Industrial: –40 °C to +85 °C  
❐ Automotive-A: –40 °C to +85 °C  
❐ Automotive-E: –40 °C to +125 °C  
■ Wide voltage range: 2.20 V to 3.60 V  
■ Pin compatible with CY62136V, CY62136CV30/CV33, and  
CY62136EV30  
■ Ultra low standby power  
❐ Typical standby current: 1 A  
❐ Maximum standby current: 5 A (Industrial)  
■ Ultra low active power  
❐ Typical active current: 1.6 mA at f = 1 MHz (45 ns speed)  
Write to the device by taking Chip Enable (CE) and Write Enable  
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data  
from I/O pins (I/O0 through I/O7) is written into the location  
specified on the address pins (A0 through A16). If Byte High  
Enable (BHE) is LOW, then data from I/O pins (I/O8 through  
I/O15) is written into the location specified on the address pins  
(A0 through A16).  
■ Easy memory expansion with CE and OE features  
■ Automatic power down when deselected  
■ Complementary metal oxide semiconductor (CMOS) for  
optimum speed and power  
■ Available in Pb-free 48-ball very fine-pitch ball grid array  
(VFBGA) and 44-pin thin small outline package (TSOP) II  
packages  
Read from the device by taking Chip Enable (CE) and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If  
Byte Low Enable (BLE) is LOW, then data from the memory  
location specified by the address pins appears on I/O0 to I/O7. If  
Byte High Enable (BHE) is LOW, then data from memory  
appears on I/O8 to I/O15. See the Truth Table on page 11 for a  
complete description of read and write modes.  
For a complete list of related resources, click here.  
Logic Block Diagram  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
128 K x 16  
RAM Array  
I/O0–I/O7  
I/O8–I/O15  
A2  
A1  
A0  
BHE  
WE  
CE  
OE  
BLE  
COLUMN DECODER  
198 Champion Court  
Cypress Semiconductor Corporation  
•
•
San Jose, CA 95134-1709  
•
408-943-2600  
Document Number: 001-08402 Rev. *O  
Revised January 2, 2018  
1234567...18

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