Datasheet > CY2LL842

CY2LL842

更新时间： 2024-11-19 23:44:59

品牌	Logo	应用领域
其他 - ETC		时钟
页数	文件大小	规格书
14页	163K
描述
Clocks and Buffers

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中文翻译

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数据手册

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CY2LL842 数据手册

ComLink™ Series

CY2LL842

Two-channel LVDS Repeater/Mux

Features

Description

• ANSI TIA/EIA-644-1995-compliant

• Does not exceed Belcore 802.3 standards

• Operation at => 350 MHz–700 Mbps

• Single 2 × 2

• Low-voltage differential signaling (LVDS) with output

voltages of ± 350 mV into 100-ohm load version (Std)

• Single 3.3V supply

• Accepts ± 350 mV differential inputs

• Output drivers are high-impedance when disabled or

when V_DD≤ 1.5V

• 16-pin SOIC/TSSOP packages

• Industrial version available

The CYPRESS CY2LL842 are differential line drivers and

receivers that utilize LVDS to achieve signaling rates of 650

Mbs. The receiver outputs can be switched to either or both

drivers thru the multiplexer control signals S0/S1. This

provides flexibility in application for either a splitter or router

configuration with a single device.

The CYPRESS CY2LL842 is configured as

two-channel repeater/Mux.

a single

The LVDS standard provides a minimum differential output

voltage of 247 mV into a 100-ohm load and receipt of as little

as 100-mV signals with up to 1V of DC offset between trans-

mitter and receiver.

A doubly terminated bus LVDS line enables multipoint config-

urations.

Designed for both point to point based-band multi-point data

transmission over controlled impedance lines.

Block Diagram

Pin Configuration

VDD

1DE

VDD

1DE

2DE

GND

2DE

S0 S1

16 pin SOIC/TSSOP

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07063 Rev. *A

Revised December 15, 2002

12 3 4 5 6 7...14

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